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ip100a lf preliminary data sheet 1/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 integrated 10/100 ethernet mac + phy features single chip 10/100base, half or full duplex ethernet media access controller ieee 802.3 compliant 100base-tx/100base-fx/10base-t pci bus master scatter/gather dma on any byte boundary full operation with pci clock from 25 mhz to 33 mhz pci revision 2.2 compliant on-chip transmit and receive fifo buffers on-chip led drivers power management capab ilities for acpi 1.0 compliant systems wakeonlan support management statistics gathering ip multicast receive and filter support using 64 bit hash table transmit polling auto pad insertion for short packets programmable minimum inter packet gap supports auto mdi-mdix function smart cable analyzer (sca) support capable of using 93c46 eeprom on-chip crystal oscillator on-chip voltage regulator 2.5/3.3v cmos with 5v tolerant i/o 0.25m technology 128-pin pqfp support lead free package (please refer to the order information) general description the ip100a lf is a single-chip, full duplex, 10/100mbps ethernet mac + phy incorporating a 32-bit pci with bus master support. the ip100a lf is designed for use in a variety of applications including workstation nics, pc motherboards, and other systems utilizing a pci bus that require network connectivity to an ethernet or fast ethernet lan. the ip100a lf includes a pci bus interface unit, ieee 802.3 compliant mac, transmit and receive fifo buffers, ieee 802.3 compliant 100base-tx, 10base-t, and 100base-fx phy, serial eeprom interface and led drivers. the ip100a lf implements a rich set of control and status registers. accessible via the pci interface, these register s provide a host system visibility into the featur es and operating state of the ip100a lf. network management statistics are also recorded, and host access to registers of the phy device are facilitated through the ip100a lf?s pci interface. the ip100a lf supports features for use in ?green pcs? or system s where control over system power consumption is desired. the ip100a lf supports several power down states, and the ability to issue a system ?wake event? via reception of unique, user defined ethernet frames. in addition, the ip100a lf can assert a wake event in response to changes in the ethernet link status
ip100a lf preliminary data sheet block diagram pci bus interface media access control (mac) physical layer (pcs, pma, pmd) txdma logic rxfifo txfifo rxdma logic pci mdi rstn reqn pmen intan idsel gntn pciclk irdyn framen par cben[3:0] ad[31..0] perrn stopn devseln trdyn x2 x1 vdet serrn iset ctrl25 test vcc2 vcc1 avcc25 avcc33 miscellaneous rstn txp ffsd rxn rxp txn eecs eesk eedi eedo led_txn led_100n led_10n led_link eeprom led led_rxn leddplxn gnd last_gasp eeop figure 1: ip100a lf block diagram march. 30, 2007 2/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 3/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 contents features ....................................................................................................................................................... 1 general description ..................................................................................................................................... 1 block diagram ............................................................................................................................................. 2 contents ...................................................................................................................................................... 3 revision history ........................................................................................................................................... 6 1 pin designations .................................................................................................................................. 7 2 pin diagram .......................................................................................................................................... 8 3 pin descriptions ................................................................................................................................... 9 pin descriptions (continued) ................................................................................................................... 10 pin descriptions (continued) ................................................................................................................... 11 4 acronyms and glossary ...................................................................................................................... 13 5 standards compliance ........................................................................................................................ 13 6 functional description ........................................................................................................................ 13 6.1 media access control ............................................................................................. 13 6.2 physical layer ........................................................................................................ 14 6.3 on-chip voltage regulator ..................................................................................... 14 6.4 pci bus interface .................................................................................................... 14 6.5 txdma logic .......................................................................................................... 14 6.6 txfifo .................................................................................................................... 15 6.7 rxdma logic .......................................................................................................... 15 6.8 rxfifo ................................................................................................................... 15 6.9 eeprom interface ................................................................................................. 15 7 operation ............................................................................................................................... ............. 16 7.1 initialization ............................................................................................................. 16 7.2 register programming ............................................................................................ 16 7.3 txdma and frame transmission ........................................................................... 17 7.4 frame reception and rxdma ................................................................................ 19 7.5 interrupts ................................................................................................................. 22 8 statistics ............................................................................................................................... ............... 22 8.1 transmit statistics .................................................................................................. 22 8.2 receive statistics ................................................................................................... 23 9 pci bus master operation .................................................................................................................. 23 10 power management ............................................................................................................................ 24 10.1 wake event ............................................................................................................. 27 10.2 power down ........................................................................................................... 27 11 registers and data structures ............................................................................................................ 28 11.1 phy registers ........................................................................................................ 28 11.1.1 control register ...................................................................................................... 28 11.1.2 status register ....................................................................................................... 29 11.1.3 phy identifier 1 ....................................................................................................... 30 11.1.4 phy identifier 2 ....................................................................................................... 30 11.1.5 auto-negotiation advertisement ............................................................................. 31 11.1.6 auto-negotiation link partner ability ...................................................................... 31 11.1.7 phy specification control register ......................................................................... 32 11.1.8 phy debug control register ................................................................................... 33 11.1.9 phy status monitor register ................................................................................... 33 11.1.10 sca settings .......................................................................................................... 34 11.2 dma data structures .............................................................................................. 35 11.2.1 rxdmafragaddr .................................................................................................... 35 11.2.2 rxdmafraglen ...................................................................................................... 36 11.2.3 rxdmanextptr ....................................................................................................... 36 11.2.4 rxframestatus ....................................................................................................... 36
ip100a lf preliminary data sheet 4/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.2.5 txdmafragaddr ..................................................................................................... 38 11.2.6 txdmafraglen ...................................................................................................... 38 11.2.7 txdmanextptr ........................................................................................................ 38 11.2.8 txframecontrol ...................................................................................................... 39 11.3 wake event data structures .................................................................................. 40 11.3.1 magicsequence ...................................................................................................... 41 11.3.2 magicsyncstream ................................................................................................... 41 11.3.3 pseudocrc ............................................................................................................ 41 11.3.4 pseudopattern ........................................................................................................ 42 11.3.5 terminator ............................................................................................................... 42 11.4 lan i/o registers ................................................................................................... 43 11.4.1 asicctrl .................................................................................................................... 44 11.4.2 dmactrl .................................................................................................................. 48 11.4.3 eepromctrl .............................................................................................................. 50 11.4.4 eepromdata ............................................................................................................ 51 11.4.5 fifoctrl .................................................................................................................. 51 11.4.6 hashtable ............................................................................................................... 52 11.4.7 intenable ................................................................................................................. 52 11.4.8 intstatus .................................................................................................................. 53 11.4.9 intstatusack ............................................................................................................ 54 11.4.10 macctrl0 ................................................................................................................ 55 11.4.11 macctrl1 ................................................................................................................ 56 11.4.12 maxframesize ........................................................................................................ 58 11.4.13 phyctrl .................................................................................................................... 58 11.4.14 receivemode .......................................................................................................... 59 11.4.15 rxdmaburstthresh ................................................................................................ 59 11.4.16 rxdmalistptr ......................................................................................................... 60 11.4.17 rxdmapollperiod ................................................................................................... 60 11.4.18 rxdmastatus ......................................................................................................... 60 11.4.19 rxdmaurgentthresh ............................................................................................. 61 11.4.20 stationaddress ....................................................................................................... 62 11.4.21 txdmaburstthresh ................................................................................................ 62 11.4.22 txdmalistptr .......................................................................................................... 63 11.4.23 txdmapollperiod ................................................................................................... 63 11.4.24 txdmaurgentthresh .............................................................................................. 64 11.4.25 txreleasethresh ................................................................................................... 64 11.4.26 txstatus .................................................................................................................. 65 11.4.27 wakeevent .............................................................................................................. 66 11.5 statistic registers ................................................................................................... 67 11.5.1 broadcastframesreceivedok ................................................................................ 67 11.5.2 broadcastframestransmittedok ............................................................................ 67 11.5.3 carriersenseerrors ................................................................................................. 68 11.5.4 framesabortedduetoxscolls ............................................................................... 68 11.5.5 frameslostrxerrors ............................................................................................... 69 11.5.6 framesreceivedok ................................................................................................ 69 11.5.7 framestransmittedok ............................................................................................ 70 11.5.8 frameswithdeferredxmission ................................................................................ 70 11.5.9 frameswithexcessivedeferal ................................................................................. 71 11.5.10 latecollisions ......................................................................................................... 71 11.5.11 multicastframesreceivedok .................................................................................. 72 11.5.12 multicastframestransmittedok .............................................................................. 72 11.5.13 multiplecollisionframes .......................................................................................... 73 11.5.14 octetsreceivedok .................................................................................................. 73 11.5.15 octetstransmittedok .............................................................................................. 74 11.5.16 singlecollisionframes ............................................................................................ 74
ip100a lf preliminary data sheet 5/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6 lan pci configuration registers ........................................................................... 75 11.6.1 cachelinesize ........................................................................................................ 76 11.6.2 capid ...................................................................................................................... 76 11.6.3 capptr ..................................................................................................................... 76 11.6.4 cispointer ............................................................................................................... 77 11.6.5 classcode .............................................................................................................. 77 11.6.6 configcommand ..................................................................................................... 78 11.6.7 configstatus ........................................................................................................... 79 11.6.8 data ........................................................................................................................ 80 11.6.9 deviceid .................................................................................................................. 80 11.6.10 exprombaseaddress ............................................................................................. 81 11.6.11 headertype ............................................................................................................ 81 11.6.12 interruptline ............................................................................................................ 82 11.6.13 interruptpin ............................................................................................................. 82 11.6.14 iobaseaddress ....................................................................................................... 82 11.6.15 latencytimer .......................................................................................................... 83 11.6.16 maxlat .................................................................................................................... 83 11.6.17 membaseaddress .................................................................................................. 83 11.6.18 mingnt .................................................................................................................... 84 11.6.19 nextitemptr ............................................................................................................. 84 11.6.20 powermgmtcap ...................................................................................................... 85 11.6.21 powermgmtctrl ....................................................................................................... 86 11.6.22 revisionid ............................................................................................................... 86 11.6.23 subsystemid ........................................................................................................... 87 11.6.24 subsystemvendorid ............................................................................................... 87 11.6.25 vendorid ................................................................................................................. 87 11.7 eeprom data format ........................................................................................... 88 11.7.1 asicctrl .................................................................................................................... 88 11.7.2 configparm ............................................................................................................. 89 11.7.3 functionsctrl ........................................................................................................... 90 11.7.4 stationaddress ....................................................................................................... 90 11.7.5 subsystemid ........................................................................................................... 91 11.7.6 subsystemvendorid ............................................................................................... 91 12 signal requirements ........................................................................................................................... 92 12.1 absolute maximum ratings .................................................................................... 92 12.2 operating ranges ................................................................................................... 92 12.3 ac characteristics .................................................................................................. 94 12.4 thermal data .......................................................................................................... 96 13 order information ............................................................................................................................... .96 14 physical dimensions ........................................................................................................................... 97
ip100a lf preliminary data sheet 6/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 revision history revision number date revision version 1.0 2003-06-25 first release version 10 2005-01-25 1. add the order information for lead free package. version 11 2005-03-14 1. modify pin name of pin 17,18,20,21,22,24,35,43,48,49 version 12 2005-04-22 1. describe eepromctrl register bit 12 and bit 13 in detail version 13 2005-05-19 1. add ip100a thermal data version 14 2005-10-20 1. remove 93c56 and eeop support. 2. modify ffsd pin definition, in page 11. version 15 2006-04-27 1. add ?support au to mdi-mdix function? description version 16 2006-10-18 1. modify rxdmalastfrag pin description, in page 36. version 17 2007-03-30 1. modify pin diagram in page 8. 2. modify led_link pin type in page 11
ip100a lf preliminary data sheet 7/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 1 pin designations pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 33 gnd 65 gnd 97 gnd 2 ad5 34 iset 66 vcc2 98 nc 3 ad4 35 avss 67 pciclk 99 vcc2 4 ad3 36 txp 68 reqn 100 framen 5 nc 37 txn 69 ad31 101 irdyn 6 ad2 38 nc 70 ad30 102 trdyn 7 ad1 39 avcc25 71 ad29 103 devseln 8 nc 40 nc 72 ad28 104 stopn 9 ad0 41 rxp 73 ad27 105 perrn 10 nc 42 rxn 74 vcc2 106 vcc1 11 vcc2 43 avss 75 gnd 107 serrn 12 nc 44 avcc25 76 ad26 108 par 13 gnd 45 ctrl25 77 ad25 109 gnd 14 led_link 46 avss 78 gnd 110 gnd 15 nc 47 avcc33 79 ad24 111 vcc2 16 led_txn 48 nc 80 cben3 112 cben1 17 eesk / led_10n 49 nc 81 vcc1 113 ad15 18 eedi / led_100n 50 nc 82 idsel 114 ad14 19 gnd 51 nc 83 ad23 115 ad13 20 nc 52 nc 84 ad22 116 ad12 21 led_rxn 53 nc 85 ad21 117 ad11 22 eedo /led_dplxn 54 nc 86 ad20 118 ad10 23 gnd 55 nc 87 gnd 119 nc 24 vcc1 56 nc 88 ad19 120 vcc1 25 test 57 nc 89 gnd 121 vcc2 26 nc 58 nc 90 ad18 122 gnd 27 nc 59 intan 91 vcc2 123 ad9 28 eecs 60 vdet 92 vcc1 124 ad8 29 nc 61 rstn 93 ad17 125 cben0 30 last_gaspn 62 gntn 94 nc 126 ad7 31 x2 63 pmen 95 ad16 127 ad6 32 x1 64 nc 96 cben2 128 ffsd table 1 : ip100a lf pin designations
ip100a lf preliminary data sheet 2 pin diagram 1 2 9 8 7 6 5 4 3 10 11 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 nc ad5 ad4 ad3 nc ad2 ad1 nc ad0 nc vcc2 nc gnd led_link nc led_txn eesk / led_10n eedi / led_100n gnd nc led_rxn eedo / led_dplxn gnd vcc1 test nc nc eecs nc last_gaspn x2 x1 gnd iset avss txp txn nc trdyn irdyn framen vcc2 nc gnd cbe2n ad16 nc ad17 vcc1 vcc2 ad18 gnd ad19 gnd ad20 ad21 ad22 ad23 idsel vcc1 cbe3n ad24 gnd ad25 ad26 gnd vcc2 ad27 ad28 ad29 ad30 ad31 reqn pciclk vcc2 gnd nc pmen gntn rstn vdet intan nc nc nc nc nc nc nc nc nc nc nc avcc33 avss ctrl25 avcc25 avss rxn rxp nc avcc25 ffsd ad6 ad7 cbe0n ad8 ad9 gnd vcc2 vcc1 nc ad10 ad11 ad12 ad13 ad14 ad15 cbe1n vcc2 gnd gnd par serrn vcc1 perrn stopn devseln ic plus corp. ip100a lf fast ethernet nic chip march. 30, 2007 8/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 9/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 3 pin descriptions pin name pin type pin description pci interface rstn input reset, asserted low. rstn will cause the ip100a lf to reset all of its functional blocks. rstn must be asserted for a minimum duration of 10 pciclk cycles. pciclk input pci bus clock. this clock is used to drive the pci bus interfaces and the internal dma logic. all bus signals are sampled on the rising edges of pciclk. pciclk can operate from 25mhz to 33mhz. gntn input pci bus grant, asserted low. gntn signals access to the pci bus has been granted to ip100a lf. idsel input initialization device select. the idsel is used to select the ip100a lf during configuration read and write transactions. intan output interrupt request, asserted low. the ip100a lf asserts intan to request an interrupt, when any one of the programmed interrupt event occurs. pmen output wake event, assertion level is program mable (see the wakepolarity bit of the wakeevent register). the ip100a lf asserts pmen to signal the detection of a wake event. reqn output request, asserted low. the ip100a lf asserts reqn to request pci bus master operation. ad [31..0] in/out pci bus address/data. address and data are multiplexed on the ad pins. the ad pins carry the physical address during the first clock cycle of a transaction, and carry data during the subsequent clock cycles. cben [3..0] in/out pci bus command/byte enable, asse rted low. bus command and byte enables are multiplexed on the cben pins. cben specify the bus command during the address phase tr ansaction, and carry byte enables during the data phase. par in/out parity. pci bus parity is even acro ss ad[31..0] and cben[3..0]. the ip100a lf generates par during addr ess and write data phases as a bus master, and during read data phase as a target. it checks for correct par during read data phase as bus master , during every address phase as a bus slave, and during write data phases as a target. framen in/out pci bus cycle frame, asserted low. framen is an indication of a transaction. it is asserted at the beginni ng of the address phase of the bus transaction and de-asserted before the final transfer of the data phase of the transaction. irdyn in/out initiator ready, asserted low. a bus master asserts irdyn to indicate valid data phases on ad[31..0] during write data phases, indicates it is ready to accept data during read data phases. a target will monitor irdyn. trdyn in/out target ready, asserted low. a bus targ et asserts trdyn to indicate valid read data phases, and to indicate it is ready to accept data during write data phases. a bus mast er will monitor trdyn. stopn in/out stop, asserted low. stopn is driven by the slave target to inform the bus master to terminate the current transaction. table 2 : ip100a lf pin descriptions
ip100a lf preliminary data sheet 10/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 pin descriptions (continued) pin name pin type pin description pci interface (continued) perrn in/out parity error, asserted low. the ip100a lf asserts perrn when it checks and detects a bus parity errors. when it is generating par output, the ip100a lf monitors for any reported parity error on perrn. serrn output system error, asserted low. vdet input power detect. the ip100a lf detects pci bus power supply loss when vdet is low. eeprom interface eecs output eeprom chip select. eecs is asserted by the ip100a lf to access the eeprom. eecs is connected directly to the chip select input of the eeprom device. eesk output eeprom serial clock. eesk is an output connected directly to the clock input of the eeprom device. eedi output eeprom data input. eedi is an output conn ected directly to the data input of the eeprom device. this pi n is shared with led100n pin. eedo input eeprom data output. eedo is an input connected directly to the data output of the eeprom device. this pin is shared with duplex led pin. led drivers led_txn output transmit status led. this pin will stay low during transmission period and high if no data or pulse is beening sent from ip100a lf. led_rxn output receiving status led. this pin will stay low during receiving period and if no data has been received, the led_rxn status will be high. led_dplxn output duplex status led. led_dplxn is the duplex status led driver. the duplex status led driver is low w hen the link is full duplex, and high when the link is half duplex. additional functionality of the speed status led signal is based on the ledmode bit of the asicctrl register. table 2 : ip100a lf pin descriptions
ip100a lf preliminary data sheet 11/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 pin descriptions (continued) pin name pin type pin description led drivers (continued) led_10n output 10mb/sec connection status led. this pin will output low to indicate 10mb/sec transmission if the co nnection between 2 devices have negoatiated to link at 10mb/sec. led_100n output 100mb/sec connection status led. this pin will output low to indicate 100mb/sec transmission if the co nnection between 2 devices have negoatiated to link at 100mb/sec. led_link output link status led. led_link is the link status led driver. the functionality of the link status led signal is bas ed on the ledmode bit of the asicctrl register. a 4.7k pull-down resistor is placed between this pin and gnd regardless of whether the led is connected to this pin. mdi rxp input receive input. when in 100base-tx m ode, this receives mlt3 data from the isolation transformer. when in 100 base-fx mode, this is a pecl input. rxn input receive input. when in 100base-tx m ode, this receives mlt3 data from the isolation transformer. when in 100 base-fx mode, this is a pecl input. txp output transmit output. when in 100base-tx mode, this is an mlt-3 driver. when in 100base-fx mode, th is is a pecl driver. txn output transmit output. when in 100base-tx mode, this is an mlt-3 driver. when in 100base-fx mode, th is is a pecl driver. ffsd input this pin is used to select tp or fiber mode. for 100base-fx applications, ffsd is connected to the signal detect output pin of a fiber optic module at pecl level. connecting this pin to gnd will force the ip100a into tp mode. miscellaneous ctrl25 output this is a controller pin to monitor correct 2.5v supply to ic. last_gaspn input this pin monitors the pci voltage. if the voltage is dropped to certain value, last_gaspn will indicate ip100a lf to transmit last gasp frame to inform the other end that ip100a lf is not functioning till system power on or reset. x1 oscin 25mhz crystal oscillator input. the ex ternal 25mhz crystal and capacitor is connected to the on-chip crystal oscillator circuit through x1 input. alternately, x1 can be driven by an external clock source. x2 oscout 25mhz crystal oscillator output. the external crystal and capacitor is also connected to the output of the on-chip crystal oscillator circuit through x2. when x1 is driven by an external clock source, x2 should be left unconnected. iset analog band gap resistor. connect a 6.2kohm, 1% resister between iset and gnd. test input test. enables the ip100a lf test modes. nc reserved. these pins must keep floating at application circuit. power and ground vcc2 power +3.3 volt i/o power supply. vcc1 power +2.5 volt digital logic power supply. avcc25 power +2.5 volt analog power supply. avcc33 power +3.3 volt analog power supply. avss ground analog ground
ip100a lf preliminary data sheet 12/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 pin name pin type pin description gnd ground power return. table 2 : ip100a lf pin descriptions
ip100a lf preliminary data sheet 13/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 4 acronyms and glossary lan local area network mac media access control layer, or a device im plementing the functions of this layer (a media access controller) pci peripheral component interface nic network interface cards fifo first in first out eprom erasable programmable read only memory eeprom electrically erasable programmable read only memory led light emitting diode phy physical layer, or device implem enting functions of the physical layer csma/cd carrier sense multiple access with collision detect fcs frame check sequence sfd start of frame delimiter crc cyclic redundancy check ip internet protocol tfd transmit frame descriptor rfd receive frame descriptor dma direct memory access acpi advanced configuration and power management 5 standards compliance the ip100a lf implements functionality compliant with the following standards: ? ieee 802.3 fast ethernet ? ieee 802.3 full duplex flow control ? pci local bus revision 2.2 ? pci bus power management interface revision 1.1 ? acpi revision 1.0 6 functional description the ip100a lf is composed of various functional bl ocks as shown in figure 1 on page 2. an overview of the functions performed by each block are as follows: 6.1 media access control the mac block implements the ieee ethernet 802.3 media access cont rol functions with 802.3 full duplex and flow control enhancements. in half duplex mode, the mac implements the csma/cd algorithm. full duplex mode by definition does not ut ilize csma/cd, allowing data to be transmitted on demand. an optional flow control mechanism in full duplex mode is provided via the mac control pause function. additionally, the mac also performs the followi ng functions in either half or full duplex mode: ? optional transmit fcs generation ? padding to the minimum legal frame size ? preamble and sfd generation ? preamble and sfd removal ? receive frame fcs checking and optional fcs stripping ? receive frame destination address matching ? support for multicast and broadcast frame reception or rejection (via filtering) ? selective interframe gap to avoid capture effect ? mac loopback the mac is responsible for generation of hardware si gnals to update the internal statistics counters.
ip100a lf preliminary data sheet 6.2 physical layer the ip100a lf supports both ieee 802.3 100base- tx and 100base-fx signaling. the 100base-x transmit logic performs 4b5b encoding/decoding, paralle l to serial, and serial to parallel conversion, and nrz-nrzi signaling. in the case of 100base-tx, scrambling and mlt- 3 encoding are also done before the data is transmitted on to the media. the receive 100base-x circuitry, recoveri ng data from either an mlt-3 signal (100base-tx) or a pecl input (100base-fx), generates four bit nibbles to send to the mac. the media dependent interface selection is done by t he ffsd pin. if the ffsd pin is connected directly to gnd, the ip100a lf phy layer is operating in tx mode. if ffsd is connected to the signal detect, then the phy layer is in 100base-fx mode. the ip100a lf phy also includes a full set of regi sters for controlling the phy as outlined in the ieee 802.3 specification. 6.3 on-chip voltage regulator the ip100a lf has an integrated voltage regulator fo r reduced system cost. the voltage regulator is used to provide the 2.5 v power to the pcb. when used wi th a 2n2905 pnp transistor based circuit as shown in figure 2, the ctrl25 pin will regulate the current through the transistor, providing a stable 2.5 v reference. ip100a lf ctrl25 voltage comparator inside ic vcc2 vcc1 mmbt2907a 150 33 0.1u 2.0k, 1% 2.2k, 1% figure 2: external pnp transistor based regulator circuit 6.4 pci bus interface the pci bus interface implements the protocols and signals needed to operate the ip100a lf in a pci bus. the ip100a lf can be either a pci bus master or slave. the pci bus interface is also responsible for managing the dma interfaces and the host processors access to the ip100a lf registers. arbitration logic within the pci bus interface block accepts bus requests from the txdma logic and rxdma logic. the pbi also manages interrupt generation for a host processor. 6.5 txdma logic the ip100a lf supports a multi-frame, multi-fragm ent dma gather process. descriptors representing frames are built and linked in system memory by a host processor. the txdma logic is responsible for transferring the multi-fragment frame data from the host memory into the txfifo. the txdma logic monitors the amount of free space in the txfifo, and uses this value to decide when to request a txdma. a txdmaburstthresh register is used to delay the bus request until there is enough free space in the txfifo for a long burst. march. 30, 2007 14/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 15/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 to prevent a txfifo under run condition the txdma logic forwards an urgent request to the arbiter, regardless of the txdmaburstthresh constraint, when the number of occupi ed bytes in the txfifo drops below the value in txdmaurgentthresh register. 6.6 txfifo the ip100a lf uses 2k bytes of transmit data buffer between the txdma logic and transmit mac. when the txdma logic determines there is enough s pace available in the txfifo, the txdma logic will move any pending frame data into the txfifo. the txreleasethresh register value determines the amount of data which must be transmitted out of the tx fifo before the fifo memory space occupied by that data can be released fo r use by another frame. a txreleaseerror occurs when a fr ame experiences a collision after t he txfifo release threshold has been crossed. the ip100a lf will not be able to retran smit this frame from the txfifo and the complete frame must be transferred from the host system memory to the txfifo again by txdma logic. 6.7 rxdma logic the ip100a lf supports a multi-frame, multi-fragment dma scatter process. descriptors representing frames are built and linked in system memory by the host processor. the rxdma logic is responsible for transferring the frame data from the rxfifo to the host memory. the rxdma logic monitors the number of bytes in the rxfifo. after a number of bytes have been received, the frame is ?visible?. a frame is visible if: ? the frame being received is determined not to be a runt, or ? the entire frame has been received after a frame becomes visible, the rxdma logic will i ssue a request to the arbiter when the number of bytes in the rxfifo is greater than the value in t he rxdmaburstthresh. to prevent receive overruns, a rxdma urgent request is made when the amount of fr ee space in the rxfifo falls below the value in rxdmaurgentthresh. 6.8 rxfifo the ip100a lf uses 2k bytes of receive data buffer between the receive mac and rxdma logic. the values in rxdmaburstthresh determine how many by tes of a frame must be received into rxfifo before rxdma logic is allowed to begin data transfer. 6.9 eeprom interface the external serial eeprom is used for non-volatil e storage of such inform ation as the node address, system id, and default configuration settings. as part of initialization after system reset, the ip100a lf reads from the eeprom and places the data into certai n host-accessible registers. ip100a lf is able to read and write to 93lc46 series eeprom. the co rrect connection is sh own in section 17.2.
ip100a lf preliminary data sheet 16/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 7 operation 7.1 initialization the ip100a lf provides several resets. the assertion of the hardware reset signal on the pci bus causes a complete reset of the ip100a lf. a similar reset is available via software using the globalreset bit of the asicctrl register. the asicctrl register al so allows for selective reset of particular functional blocks of the ip100a lf. see the registers and data structures section for details on using the asicctrl register for resetting the ip100a lf. shortly after reset, the ip100a lf will read the cont ents of an external eeprom, placing the data read into the following registers: ? configparm ? asicctrl (least significant 16 bits) ? subsystemvendorid ? subsystemid ? stationaddress ? data there are several other registers which must be config ured by the host during initialization. these registers include the ip100a lf pci configuration registers wh ich are set during a power on self test (post) routine performed by the host system. specifically, the registers set during this stage of initialization are: ? configcommand enables adapter operation by allowing it to respond to and generate pci bus cycles. configcommand is also used to enable parity error generation. ? lobaseaddress sets the i/o base address for the ip100a lf registers. ? membaseaddress sets the memory base address for the ip100a lf registers. ? exprombaseaddress sets the base address and size for an installed expansion rom, if any. ? cachelinesize indicates the system?s cache line size. this value is used by the ip100a lf to optimize bus master data transfers. ? latencytimer sets the length of time the ip 100a lf can hold the pci bus as a bus master. ? interruptline maps ip100a lf?s interrupt request to a specific interrupt line (level) on the system board. ? asicctrl is used to setup internal operations and parameters. the ip100a lf can be accessed across the pci bu s without setting the pci registers or loading data from an external eeprom. in this fo rced configuration mode (useful for embedded applications without an eeprom), the ip100a lf is configured as follows: ? i/o base address 0x200 ? i/o target cycles enabled ? memory target cycles disabled ? bus master cycles enabled 7.2 register programming after initialization, an additional set of registers spec ific to operation of the ethernet network must be programmed. the first setting relates to the auto-negotiation function. the ip100a lf phy layer performs the auto-negotiation process, and the host system must communicate with the phy to determine the link status. once the result of auto -negotiation is determined, if a full duplex mode has been chosen, the host system must set the fullduplexenable bit in the macctrl0 register. other modes chosen during auto-negotiation do not require any ip100a lf register settings. the receivemode register determines which types of frames, based on address matching mechanism, the ip100a lf will receive. the end station address is loaded from t he eeprom, or the host system can
ip100a lf preliminary data sheet set the address directly. then, by setting the receiveu nicast bit in the receivemode register, the ip100a lf will receive unicast frames whose destination address matches the value in the stationaddress register. the receivemulticasthash bit in receivemode enables a filtering mechanism for ethernet multicast frames. this filtering mechanism uses a 64-bit hash t able (hashtable register) fo r selective reception of ethernet multicast frames. additionally, ethernet frames containing ip multicas t destination addresses c an also be received by setting the receiveipmulticast bit in the receivemode register. ip multicast, or host extension for ip multicasting, datagrams map to frames with ether net destination addresses of 0x01005e****** (where * represents any hexadecimal value). the macctrl0 and macctrl1 registers are used to c onfigure parameters including full duplex, flow control, and statistics gathering. in half duplex mode, the ip100a lf implements the cs ma/cd algorithm. if multiple nodes on the same network attempt to transmit simult aneously, a collision will occur result ing in re-transmission. in full duplex mode, the ip100a lf can transmit and receive frames simultaneously without incurring collisions. to configure the ip100a lf for full duplex mode op eration, the host system must detect a full duplex physical link via the phy status register, and mu st set the fullduplexenable bit in the macctrl0 register. the ieee 802.3x full duplex standard defines a special frame kn own as the pause mac control frame. the pause frame is used to implement flow control in full duplex networks allowing stations on opposite ends of a full duplex link the ability to inhibit transmi ssion of data frames for a specified period of time. the pause frame format is defined as shown in figure 3. da sa type opcode pause time pad field 6 6 2 2 2 42 0x0180c2000001 0x8808 0x0001 length (bytes) figure 3: pause frame whenever the flowcontrolenable bit in the macctrl0 register is set, the ip100a lf looks for any incoming pause frame. if found, the ip100a lf inhibits transmission of all data frames for the time specified in the two-byte pause_time fi eld. the pause_time field is specified in slot times relative to the current data rate; one slot time is 51.2 us at 10 mbps, and 5.12 us at 100 mbps. the transmission of pause frames is the responsibility of the host. the mac control frame must be constructed by the host and placed into the txfifo. for end station applications, host system should only accept pause frames, and not generate them. flow control is designed to originate from network devices such as switches. 7.3 txdma and frame transmission the txdma logic transfers frame data from the ho st system memory to the ip100a lf based on a march. 30, 2007 17/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet linked list of frame descriptors called tfds. the host system creates a list of tfds in system memory, where each tfd contains the memory locations of one or more fragments of a frame as shown in figure 4. host system memory txdmanextptr txframecontrol 1st txdmafragaddr 1st txdmafraglen 2nd txdmafragaddr 2nd txdmafraglen last txdmafragaddr last txdmafraglen 1st data frag (buffer) tfd 2nd data frag (buffer) last data frag (buffer) figure 4: txdma data structure the tfd format is covered in the regi sters and data structures section. the resulting linked list of tfds is referred to as the txdmalist, as shown in figure 5. host system memory tfd1 tfd2 figure 5: txdma list of two tfds march. 30, 2007 18/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 19/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 in the simple case of a single fr ame, the host system mu st create a tfd within the host system memory containing the addresses and lengths of the fragments of data to be transmitted. the host system must write zero into txdmanextptr since this is the onl y frame. the host starts the txdma logic by writing the memory location (a non-zero address) of t he tfd into txdmalistptr register. the txdma logic begins transferring data into the ip100a lf. the ip100a lf first fetches the fragment addresses and fragment lengths from the tfd and writes them one at a time into registers, which are used to control the data transfer op erations. if the txdma logic transfers more data than can fit into the txfifo, an overrun will occur. the txdmalistptr i/o register within the ip100a lf contains the physical ad dress that points to the head of the txdmalist. txdmalistptr must point to addresses which are on 8-byte boundaries. a value of zero in the txdmalistptr register implies ther e are no pending tfd?s for the ip100a lf to process. generally, it is desirable for the host system to queu e multiple frames. multiple tfd?s are linked together in a list by pointing the txdmanextptr of each tfd at the next tfd. the last tfd in the linked list should have a value of zero for it?s txdmanextptr. the txdma process returns to the idle state upon det ection of a zero value for txdmanextptr. when a new frame is available to transfer, the host system must write the address of the new tfd into the txdmanextptr memory location of the last tfd, an d either set the txenable bit, or utilize the ip100a lf?s automatic polling capability. using automatic polling, the ip100a lf will monitor the txdmanextptr memory location until a non-zero value is found at that location in system memory. the txdmapollperiod register controls this polling fu nction, which is enabled when txdmapollperiod contains a non-zero value. the value written to txdmapollperiod determines the txdmanextptr polling interval. in response to a txdmacomplete interrupt, wh en data transfer by txdma is finished, the host acknowledges the interrupt and returns the frame data buffe rs to the system. in the case of a multi-frame txdmalist, multiple frames may have been transferred by txdma when the host system enters its interrupt service routine. the host system can traverse the list of tf d?s, examining the txdmacomplete bit in each tfd to determine which frames have been transferred by txdma. the ip100a lf fetches the tfc before frame data tran sfer, and again at the end of txdma operation to examine the txdmaindicate bit. this allows the host system to change txdmaindicate while data transfer of the frame is in progress. for instance, a frame?s tf d might be at the end of the txdmalist when it starts txdma, so the host system would probably set txdmaindicate to generate an interrupt. however, if during the txdma process of this frame, the host syst em added a new tfd to the end of the list, it might clear txdmaindicate in the currently active tfd so that the interrupt is delayed until the next tfd. the ip100a lf has the ability to automatically round up the length of a transmit frame. this is useful in some nos environments in which frame lengths need to be an even number of words. the frame length is rounded up to either a word or dword boundary, dep ending upon the value of wordalign. host systems may disable frame length word-alignment by setting th e wordalign bits in the tr ansmitframecontrol to x1. the mac will initiate frame transmiss ion (if transmission is enabled) as soon as either the entire frame is resident in the txfifo register. as a frame transmits out of the txfifo, it is desirable to be able to release the fifo space so that it may be used for another frame. the value programmed into txreleasethresh determines how much of a frame must be transmitted before its fifo space can be released. 7.4 frame reception and rxdma the frame rxdma mechanism is similar to the txdma mechanism. rxdma is structured around a
ip100a lf preliminary data sheet linked list of frame descriptors, called rfds. rfds co ntain pointers to the fragment buffers into which the ip100a lf is to place receive data, as shown in figure 6. host system memory rxdmanextptr rxframestatus 1st rxdmafragaddr 1st rxdmafraglen 2nd rxdmafragaddr 2nd rxdmafraglen last rxdmafragaddr last rxdmafraglen 1st data frag (buffer) rfd 2nd data frag (buffer) last data frag (buffer) figure 6: rxdma data structure the rfd format is covered in the regi sters and data structures section. similar to tfds, the resulting linked list of rfds is referred to as the rxdmalist. one option available to rxdma that differs from txdma is that the rxdmalist can be formed into a ring as shown in figure 7. a host system can allocate a number of full size frame buffers, create a rfd for each one, and link the rfds into a circular list. as frames are received and transferred by rxdma, a rxdmacomplete interrupt will be generated for each frame. march. 30, 2007 20/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet host system memory rfd 1 rfd 2 rfd n figure 7: rxdma list shown in ring the host system must create a rxdmalist and the associ ated buffers prior to reception of a frame. one approach calls for the host system to allocate a bl ock of full size (i.e. large enough to hold a maximum size ethernet frame of 1518 bytes) frame buffers in system data space and create rfds that point to them. another approach is for the host system to requ est the buffers from the protocol ahead of time. after reset, the ip100a lf receive function is disabl ed. once the rxenable bit is set, frames will be received according to the matching mode programmed in receivemode register. reception can be disabled by setting the rxdisable bit. if set while a frame is being received, rxdisable only takes effect after the active frame reception is finished.the rece ive function begins with the rxdma logic in the idle state. the rxdma logic will begin pr ocessing a rxdmalist as soon as a non-zero address is written into the rxdmalistptr register. the host system creates a rfd with the addresses and lengths of the buffers to be used and programs the rxdmalistptr regi ster to point to the head of the list. the host system must program a zero into the rxdmanextptr of the last rfd to indicate the end of the rxdmalist. when a frame is received in the rxfi fo, the ip100a lf fetches the fragment address and fragment length values one by one from the current rfd, and writes these values into internal registers which control9 ?r? -! bjbjy?y? ` ?? ? -?? ?? ? ?? lp , , , ?? of the rfd from which the host system has finished ill either assert an implicit rxdmahalt or, if the rxdmapollperiod register is set to a non-zero value, ?? lp p p p t? reading data. if rxdmapollperiod is zero the host sy stem should also issue a rxdmaresume in case the ip100a lf has halted due to detection of a set rx dmacomplete bit within the receiveframestatus field of the next rfd in the ring. if the ip100a lf fetches a rxdmalistptr for a rfd that has already been used (a rfd in which the rxdmacomplete bit is set in receiveframestatus), the rxdma logic the ip100a lf can be configured to generate a rxdmacomplete interrupt when rxdma completes a frame transfer. in response to a rxdmacomplet e interrupt, the host system must examine the receiveframestatus field in the rfd of the received frame to determine the size of the frame and whether there were any errors. the host system must then co py the frame out of the receive buffers, if needed. w the rxdma logic will automatically recheck rxdmacompl ete periodically until it is cleared. in general, when the host system ent ers its interrupt service routine, multiple frames may have been transferred by rxdma. the host system can read rxdm alistptr to determine which rfds in the list have been used. the host system beg ins at the head of the rfd list, and traverses the list until it reaches the rfd whose address matches rxdmalistptr. however, since i/o operations are costly, it is more efficient to use the rxdmacomplete bit in each rfd to determine which frames have been transferred by rxdma. march. 30, 2007 21/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 22/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 in some host systems, it may be desirable to copy received frame data out of the scatter buffer to the protocol buffer while the frame is still being tran sferred by rxdma. the rx dmastatus register is provided for this purpose. if the host system sets the rxdmahalt bit in the dmactrl register, reads the rxdmalistptr register and the rx dmastatus register, then sets the rxdmaresume bit in the dmactrl register, the host system can determine how much of the frame has been tran sferred by rxdma. the rxdmastatus register indicates the number of byte s transferred by rxdma for the current rfd pointed to by the rxdmalistptr register. the host system can then perform me mory copies out of the rfd buffer concurrently with the rxdma operation. 7.5 interrupts the term ?interrupt? is used loosely to refer to interrupt s and indications. an interrupt is the actual assertion of the hardware interrupt signal on the pci bus. an indica tion, or a set bit in the intstatus register, is the reporting of any event enabled by the host. the host system will configure the ip100a lf to generate an interrupt for any indication that is of interest to it. t here are 10 different types of interrupt indications that can be generated by the ip100a lf. the intenable regist er controls which of the 10 indication bits can assert a hardware interrupt. in order for an indication bit to be allowed to generate an interrupt, its corresponding bit-position in intenable must be set. when responding to an interrupt, the host reads the intstatus register to determine the cause of the interrupt. the least significant bit of intstatus, interruptstatus, is always set whenever any of the inte rrupts are asserted. interruptstatus must be explicitly acknowledged (cleared) by writing a 1 into the bit in order to prevent spurious interrupts on the host bus. interrupts are acknowledged by the host carrying out various actions specific to each interrupt. 8 statistics the ip100a lf implements 16 statistics counters of va rious widths. each statistic implemented complies to the corresponding definition given in the ieee 802.3 standard. setting the statisticsenable bit in the macctrl1 register enables the gather ing of statistics. reading a statis tics register will clear the read register. statistic registers may be read without dis abling statistics gathering. for diagnostics and testing purposes, the host system may write a value to a stat istic register, in which case the value written is added to the current value of the register. whenever o ne or more of the statistics registers reaches 75% of its maximum value, an updatestats interrupt is generated. reading that statistics register will acknowledge the updatestats interrupt. a summary of the transmit and receive statistics follows. detailed descriptions of the statistic registers related to data transmission and reception can be found in the registers and data structures section. 8.1 transmit statistics ? framestransmittedok: the number frames of all ty pes transmitted without errors. loss of carrier is not considered to be an error by this statistic. ? broadcastframestransmittedok: the number of frames with broadcast des tination address that are transmitted without errors. ? multicastframestransmittedok: the number of fr ames with multicast destination address that are transmitted without errors. ? octetstransmittedok: the number of total octe ts for all frames transmitted without error. ? frameswithdeferredxmission: a count of fram es whose transmission wa s delayed on it?s first attempt because network traffic. ? frameswithexcessivedeferral: if the transmi ssion of a frame has been deferred for an excessive period of time due to network traffic, t he event is recorded in this statistic. ? singlecollisionframes: frames that are transmi tted without errors after one and only one collision (including late collisions) are counted by this register. ? multiplecollisionframes: all fr ames transmitted without error afte r experiencing from 2 through 15 collisions (including late collisions) are counted here.
ip100a lf preliminary data sheet 23/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 ? latecollisions: every occurrence of a late collision (there could be more than one per frame transmitted) is counted by this statistic. ? framesabortedduetoxscolls: if the transmission of a frame had to be aborted due to excessive collisions, the event is recorded in this statistic. ? carriersenseerrors: frames that were transmitted without error but experienc ed a loss of carrier are counted by this statistic. 8.2 receive statistics ? framesreceivedok: frames of all types t hat are received without error are counted here. ? broadcastframesreceivedok: fram es of broadcast destination addr ess that are received without error are counted here. ? multicastframesreceivedok: frames of multic ast destination address that are received without error are counted here. ? octetsreceivedok: a total octet count for all frames received without error. ? frameslostrxerrors: this is a count of frames that would otherwise be re ceived by the ip100a lf, but could not be accepted due to an ov errun condition in the rxfifo. 9 pci bus master operation the ip100a lf supports all of the pci memory co mmands and decides on a burst-by-burst basis which command to use in order to maximize bus efficiency. the list of pci memory commands is shown below. for all commands, ?read? and ?write? are with respect to the ip100a lf (i.e. read implies the ip100a lf obtains information from an off-chip location, write im plies the ip100a lf sends information to an off-chip location). ? memory read (mr) ? memory read multiple (mrm). ? memory write (mw) ? memory write invalidate (mwi) mr is used for all fetches of descriptor informati on. for reads of transmit frame data, mr, or mrm is used, depending upon the remaining number of bytes in the fragment, the amount of free space in the txfifo, and whether the rxdma logic is requesting a bus master operation. mw is used for all descriptor writes. writes of receive frame data use either mw or mwi, depending upon the remaining number of bytes in the fragmen t, the amount of frame data in the rxfifo, and whether the txdma logic is requesting a bus master operation. the ip100a lf provides three configuration bits to control the use of advanced memory commands. the mwlenable bit in the configcommand configuration register allows the host to enable or disable the use of mwi. the mwidisable bit in dmactrl allows the host system the ability to disable the use of mwi. mwidisable is cleared by default, enabling mwi. the ip100a lf provides a set of registers that cont rol the pci burst behavior. these registers allow a trade-off to be made between pci bus efficiency and under run/overrun frequency. arbitration logic within the pci bus interface block accepts bus requests from the txdma logic and rxdma logic. the txdma logic uses the txdmaburstthresh register, as described in the txdma logic section, to delay the bus request until there is enough free space in the txfifo for a long, efficient burst. the txdma logic can also make an urgent bus request as desc ribed in the txdma logic section, where burst efficiency is sacrificed in favor of avoiding a txfifo under run condition. the rxdma process is described in the rxdma logic se ction. typically, rxdma requests will be forwarded to the arbiter, however rxdma urgent requests are also possible in order to prevent rxfifo overruns.
ip100a lf preliminary data sheet 24/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 10 power management the ip100a lf supports operating system dire cted power management according to the acpi specification. power management registers in the pc i configuration space, as defined by the pci bus power management interface specificati on, revision 1.0 are described in 10.0. the ip100a lf supports several power management stat es. the powerstate field in the powermgmtctrl register determines ip100a lf?s current power state. the power states are defined as follows: ? d0 uninitialized (power state 0) is entered as a re sult of hardware reset, or after a transition from d3 hot to d0. this state is the same as d0 active except that the pci configuration registers are uninitialized. in this state, the ip100a lf is unabl e to respond to pci i/o, memory and configuration cycles and can not operate as a pci master the ip 100a lf cannot signal wake (pmen) from the d0 state. ? d0 active (power state 0) is the normal operational power state for the ip100a lf. in this state, the pci configuration registers hav e been initialized by the sy stem, including the iospace, memoryspace, and bus-master bits in configcommand, so the ip100a lf is able to respond to pci i/o, memory and configuration cycles and can operate as a pci master. the ip100a lf cannot signal wake (pmen) from the d0 state. ? d1 (power state 1) is a ?light-sleep? state. the ip100a lf optionally suppo rts this state determined by the d1support bit in the configparm word in eeprom. the d1 state allows transition back to d0 with no delay. in this state, the ip100a lf responds to pci configuration accesses, to allow the system to change the power state. in d1 the ip100a lf does not respond to any pci i/o or memory accesses. the ip100a lf?s function in the d1 stat e is to recognize wake events and link state events and pass them on to the system by asse rting the pmen signal on the pci bus. ? d2 (power state 2) is a partial power-down st ate. the ip100a lf optionally supports this state determined by the d2support bit in the configparm wo rd in eeprom. d2 allows a faster transition back to d0 than is possible from the d3 state. in this state, the ip100a lf responds to pci configuration accesses, to allow the system to ch ange the power state. in d2 the ip100a lf does not respond to any pci i/o or memory accesses. the ip100a lf?s function in the d2 state is to recognize wake events and link state events and pass them on to the system by asserting the pmen signal on the pci bus. ? d3 hot (power state 3) is the full power-down state for the ip100a lf. in d3 hot, the ip100a lf loses all pci configuration information except for t he value in powerstate. in this state, the ip100a lf responds to pci configuration accesses, to a llow the system to change the power state back to d0 uninitialized. in d3 hot, the ip100a lf does not respond to any pci i/o or memory accesses. the ip100a lf?s main responsibility in the d3 ho t state is to recognize wake events and link state events and signal those to the system by asserting the pmen signal on the pci bus. ? d3 cold (power state undefined) is the power-o ff state for the ip100a lf. the ip100a lf does not function in this state. when pow er is restored, the system guar antees the assertion of hardware reset, which puts the ip100a lf into the d0 uninitialized state. the ip100a lf can generate wake events to the system as a result of wake packet reception, magic packet reception, or due to a change in the link st atus. the wakeevent register gives the host system control over which of these events are passed to th e system. wake events are signaled over the pci bus using the pmen pin. a wake packet event is controlled by the wake pktenable bit in wakeevent register. wakepktenable has no effect when ip100a lf is in the d0 power st ate, as the wake process can only take place in states d1, d2, or d3. when the ip100a lf detects a wake packet, it signals a wake event on pmen (if pmen assertion is enabled), and sets the wakepktev ent bit in the wakeevent register. the ip100a lf can signal that a wake event has occurred when it re ceives a pre-defined frame from another station. the host system transfers a set of frame data patte rns into the transmit fifo using the transmit dma function before placing the ip100a lf in a power- down state. once powered down, the ip100a lf compares receive frames with the frame patterns in the transmit fifo. when a matching frame is received (and also passes the filtering mode set in the receivemode register), a wake event is signaled.
ip100a lf preliminary data sheet the frame patterns in the transmit fifo specify whic h bytes in received frames are to be examined. each byte in the transmit fifo specifies a four bit rela tive offset (from the start of the received frame) in the most significant nibble and a four bit length indicato r in the least significant nibble. relative offsets describe the number of bytes of t he received frame to skip from the last relevant byte, beginning with byte 0x00. relative offsets with a value of 0xf indicate the actual relative offset is larger than 15, and is specified by the next 8 bit value in the transmit fifo . length indicators with a value of 0xf indicate the actual length indicator is larger than 15, and is specif ied by the next 8 bit value in the transmit fifo. if both the relative offset, and the length indicator are 0x f, the first byte following the relative offset/length indicator pair is the actual relative offset, and the sec ond following byte is the actual length indicator. a byte value of 0x00 indicates the end of the pattern for that wake frame. immediately following the end-of-pattern is a 4-byte crc. the calculation used to for the crc is the same polynomial as the ethernet mac fcs. an example pseudo-packet (based on the arp packet example from appendix a of the ?onnow network device class power management specification? ) which would be loaded into the transmit fifo of the ip100a lf is shown in figure 8. txfifo pseudo packet 0xc2 0xf3 0x00 0x10 0xf4 0x71 0xd7 0x08 0x19 figure 8: example pseudo packet using the pseudo packet in figure 8, the ip100a lf will assert a wake event if a packet of the form shown in figure 9 is received whereby a 32-bit crc over the indicated bytes of the received packet yields the value 0xf31908d7. march. 30, 2007 25/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet received packet byte 12 byte 13 byte 21 byte 41 byte 40 byte 39 byte 38 byte offset within packet 0x0c 0x29 0x28 0x27 0x26 0x15 0x0d figure 9: example wake packet the ip100a lf also supports magic packet? te chnology developed by advanced micro devices to allow remote wake-up of a sleeping station on a netw ork via transmission of a special frame. once the ip100a lf has been placed in magic packet mode and put to sleep, it scans all incoming frames addressed to it for a data sequence consisting of 16 consecutive repetitions of its own 48-bit ethernet mac stationaddress. this sequence can be located anywhere within t he frame, but must be preceded by a synchronization stream. the synchronization stream is defined as 6 by tes of 0xff. for exampl e, if the mac address programmed into the stationaddress register is 0x11:22:33:44:55:66, then t he ip100a lf would be scanning for the frame data shown in figure 10. received packet 0xffffffffffff 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 figure 10: example magic packet magic packet wake up is controlled by the magicpkt enable bit in the wakeevent register. a wake event march. 30, 2007 26/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 27/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 can only take place in the d1, d2, or d3 states, and magicpktenable has no effect when the ip100a lf is in the d0 power state. the magic packet must also pass the address matching criteria set in receivemode. a magic packet may also be a broadc ast frame. when the ip100a lf detects a magic packet, it signals a wake event on pmen (if pmen as sertion is enabled), and se ts the magicpktevent bit in wakeevent. the ip100a lf can also signal a wake event when it senses a change in the network link state, either from link_ok to link_fail, or vice versa. link st ate wake is controlled by the linkeventenable bit in the wakeevent register. at the time linkeventenable is set by the host system, the ip100a lf samples the current link state. it then waits for the link state to change. if the link state changes before the ip100a lf returns to state d0 or linkeventenable is cleared, linkevent is set in wakeevent, and (if it is enabled) the pmen signal is asserted. 10.1 wake event when a desired wake event occurs, the ip100a lf sets the appropriate event bit in the wakeevent register, sets the pmestatus bit in the powerm gmtctrl register, and asserts the pmen signal. the host system responds to pmen by scanning th e power management configur ation registers of all devices, looking for the device which asserted pmen. if the device with the ip100a lf signaled wake, the system will find pmestatus set in ip100a lf?s powermgmtctrl register. the operating system then clears the pmeen bit in the powermgmtctrl register causing pmen to be de-asserted. the operating system raises the power state (probably to d0) by writing to the powerstate bits in the powermgmtctrl register. if the ip100a lf was previously in the d3 state, pci configuration is lost and must be restored by the operating system. the host system must set txreset to clear any wake pa tterns out of the transmit fifo (if this is not done, the patterns will be treated as frames and tr ansmitted once the tran smitter is enabled). the host system reads the wakeevent register to determine the wake event, and if requested, passes it back to the operating system. the host system restores any volatile st ate that was saved in the power down sequence. the host system re-enables interr upts by programming intenabl e. the host system restores the rxdmalist (and any other data structures required for operation). any wake packets in the receive fifo are transferred by receiv e dma and passed to the operating system. 10.2 power down d0u and d0i are mutually exclusive. the mom ent that the iobaseaddress register or the membaseaddress is written by the host, then ip100a lf enters d0u. when d0u is active, the phy is completely powered down and all clocks (asicclk, tx clk, rxclk) are gated off except pciclk. the ip100a lf consumes less than 70 ma in d0u. make sure that the led drivers are off. when ip100a lf is in d0i, the phy is powered up and ready to transmit and receive packets. in forced config mode (motherboard applications), ip100a lf is always in d0i mode. another way to indicate d0u is to check the non-zero value in the programmable field of io baseaddress or membaseaddress. in wol the phy should be fully functional to receive magic packets. in wol mode, d0u should be forced to low before passing to the phy. when in the d3 state, if pmen is de-asserted on the pci bus the ip100a lf will enter power down. when in power down mode, the ph y is completely powered down. all clocks (asicclk, txclk, rxclk) except pciclk are gated off. when the pci bus is powered down, the ip100a lf consumes less than 5 ma.
ip100a lf preliminary data sheet 28/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11 registers and data structures 11.1 phy registers the ip100a lf includes a full set of phy regist ers which can be accessed through the internal mdc/mdio interface. the mac and phy, although int egrated, act as if they are separate. the phy registers must be accessed th rought the phyctrl register. 11.1.1 control register class............................. phy registers, control access method ............ . accessed through phyctrl register register address .......... 0x00 default ............. ............. 0x3100 width ............................ 16 bits bit bit name r/w bit description 15 reset r/w 1 = software reset (self clearing). while the ip100a lf is resetting, reset will remain a logic 1 and write attempts to any phy registers are not accepted. 0 = normal operation. 14 loopback r/w 1 = phy loopback mode. when loopback is a logic 1, the ip100a lf will be isolated from the netwo rk media. all transmit data from the mac will return to t he mac as receive data. collision indications are disabled unless collision test is a logic 1. 0 = normal operation. 13 speed r/w 1 = 100 mb/s. 0 = 10 mb/s. 12 auto-negotiation r/w 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. 11 power down r/w 1 = phy power down. when power down is a logic 1, the ip100a lf phy will enter power down mode. while in power down mode, the ip100a lf phy will not respond to transmit data, or received data but will respond to management transactions. 0 = normal operation. 10 isolate r/w 1 = isolate phy. when isol ate is a logic 1, the ip100a lf phy will be isolated from the mac. when isolated, the ip100a lf will not respond to transmit or receive data, but will respond to management transactions. 0 = normal operation. 9 restart auto-negotiation r/w 1 = restart auto-negotiation (self clearing). when restart auto-negotiation is a logic 1, the ip100a lf will restart auto-negotiation, depending on the auto-negotiation bit. if the auto-negotiation bit is a logic 0, then restart auto-negotiation has no effect. 0 = normal operation. 8 duplex mode r/w 1 = full duplex. 0 = half duplex.
ip100a lf preliminary data sheet 29/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 7 collision test r/w 1 = enable col test. if collision test is a logic 1 and transmit data is sent to the phy, the ip100a lf phy will assert the collision signal within 512 bit times (where 1 bit time = 100ns for 10mbps operation and 1 bit time = 10ns for 100mbps operation). when transmit data is removed, the ip100a lf phy will deassert the collision signal within 4 bit times. 0 = normal operation. 6..0 reserved n/a reserved for future use. 11.1.2 status register class............................. phy registers access method............. accessed through phyctrl register register address.......... 0x01 default ............. ............. 0x7849 width ............................ 16 bits bit bit name r/w bit description 15 100base-t4 r 1 = phy 100base-t4 capable. 0 = phy not 100base-t4 capable. 14 100base-x full duplex r 1 = phy 100base-x half duplex capable. 0 = phy not 100base-x half duplex capable. 13 100base-x half duplex r 1 = phy 100base-x half duplex capable. 0 = phy not 100base-x half duplex capable. 12 10base-t full duplex r 1 = phy 10base-t full duplex capable. 0 = phy not 10base-t full duplex capable. 11 10base-t half duplex r 1 = phy 10base-t half duplex capable. 0 = phy not 10base-t half duplex capable. 10..7 reserved n/a reserved for future use. 6 preamble suppression r 1 = management preamble may be suppressed. 0 = management preamble required. 5 auto-negotiation complete r 1 = auto-negotiation complete. 0 = auto-negotiation not complete. if auto-negotiation complete is a logic 1, the auto-negotiation process is complete and the contents of the auto-negotiation link partner ability and auto-negotiation expansion registers are valid. if auto-negotiation complete is a logic 0, the auto-negotiation process is not complete, and the contents of the auto-negotiation link partner ability and auto-negotiation expansion registers are undefined. if the auto-negotiation bit of the control register is a logic 0, then auto-negotiation complete is always a logic 0. 4 remote fault r 1 = remote fault detected. 0 = remote fault not detected. if remote fault is a logic 1, the ip100a lf has detected a remote fault condition. remote fault will remain a logic 1 until the remote fault condition no longer exists, and remote fault is read by the host system.
ip100a lf preliminary data sheet 30/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 3 auto-negotiation ability r 1 = auto-negotiation capable. 0 = auto-negotiation incapable. if auto-negotiation ability is a logic 1, the ip100a lf is capable of performing auto-negotiation. auto-negotiation ability depends on the external mode setting of the ip100a lf. 2 link status r 1 = link is up. 0 = link is down. when link status is a logic 0, link status will remain a logic 0 until the link state changes, and link status is read by the host system. 1 jabber detect r 1 = jabber detected. 0 = jabber not detected. when jabber detect is a logic 1, jabber detect will remain a logic 0 until the jabber condition no longer exists, and jabber detect is read by the host system. 0 extended capability r 1 = extended capabilities register exists. 11.1.3 phy identifier 1 class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x02 default ............. ............. 0x0243 width ............................ 16 bits bit bit name r/w bit description 15..0 phy id number r bits 3 through 18 of the oui. oui = 0090c3 11.1.4 phy identifier 2 class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x03 default .......................... 0x0d80 width ............................ 16 bits bit bit name r/w bit description 15..10 phy id number r bits 19 through 24 of the oui. 9..4 model number r manufacturer?s model number. 3..0 revision number r four bit manufacturer?s revision number.
ip100a lf preliminary data sheet 31/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.1. 5 auto-negotiation advertisement class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x04 default .......................... 0x01e1 width ............................ 16 bits bit bit name r/w bit description 15 next page capable r/w 1 = next page capable. 0 = next page incapable. 14 reserved n/a reserved for future use. 13 remote fault r/w 1 = remote fault supported. 0 = remote fault not supported. 12..11 reserved n/a reserved for future use. 10 pause r/w 1 = pause function supported. 0 = pause not supported. 9 100base-t4 r/w 1 = 100base-t4 capable. 0 = 100base-t4 incapable. 8 100base-tx full duplex r/w 1 = phy 100base-tx full duplex capable. 0 = phy not 100base-tx full duplex capable. 7 100base-tx half duplex r/w 1 = phy 100base-tx half duplex capable. 0 = phy not 100base-tx half duplex capable. 6 10base-t full duplex r/w 1 = phy 10base-t full duplex capable. 0 = phy not 10base-t full duplex capable. 5 10base-t half duplex r/w 1 = phy 10base-t half duplex capable. 0 = phy not 10base-t half duplex capable. 4..0 selector field r/w ieee 802.3 selector field 11.1.6 auto-negotiation link partner ability class............................. phy registers access method............. accessed through phyctrl register register address.......... 0x05 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 15 next page r 1 = next page capable. 0 = next page incapable. 14 acknowledge r 1 = link code word received. 0 = link code word not received. 13 remote fault r 1 = remote fault detected. 0 = remote fault not detected. if remote fault is a logic 1, then the remote fault bit of the status register register will be a logic 1. 12..10 reserved n/a reserved for future use. 9 100base-t4 r 1 = 100base-t4 capable. 0 = 100base-t4 incapable.
ip100a lf preliminary data sheet 32/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 8 100base-tx full duplex r 1 = 100base-tx full duplex capable. 0 = not 100base-tx full duplex capable. 7 100base-tx half duplex r 1 = 100base-tx half duplex capable. 0 = not 100base-tx half duplex capable. 6 10base-t full duplex r 1 = 10base-t full duplex capable. 0 = not 10base-t full duplex capable. 5 10base-t half duplex r 1 = 10base-t half duplex capable. 0 = not 10base-t half duplex capable. 4..0 selector field r selector field 11.1.7 phy specification control register class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x16 default .......................... 0x03a4 width ............................ 16 bits bit bit name r/w bit description 15:6 reserved 5 automdix_on ro a utocrossover can be set to enabled by setting this bit to 1, even when an is disabled 4 fef_disable r/w set high to disable the fu nctionality of far-end fault when the chip operates at fiber mode 0: enable fef 1: disable fef 3 repeat_mode r/w set high to let ip100a lf operate at repeat mode 0: not repeat mode 1: repeat mode 2 jabber_ena r/w set high to enable jabber detection mechanism when ip100a lf operates at 10base-t 0: disable 1: enable 1 heartbeat_ena r/w set high to enable hear tbeat detection mechanism when ip100a lf operates at 10base-t 0: disable 1: enable 0 bypass_dsprst r/w set high to disable dsp reset watch-dog timer 0: not bypass 1: bypass
ip100a lf preliminary data sheet 33/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.1. 8 phy debug control register class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x17 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 15:6 reserved ro reserved for future use 5 nway_speed_up rw set high to speed up all timers during nway procedure 4 dsp_speed_up rw set high to sp eed up dsp training sequcences 3 force_link rw set high to force link-up 2 bypass_scram rw set high to bypass pcs scrambler/de-scrambler 1..0 nway_debug_se l rw these 2 bits are used to select nway debug output 11.1.9 phy status monitor register class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x18 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 15 ldsp_sleeping ro when set to high, indicating ip100a lf is in link-down sleeping mode 14 link_ok ro when set to high, indicating link status is ok 13 descram _lock ro when set to high, indicating pcs de-scrambler is locked on data 12 10base_ polarity ro when set to high, indicating the cable polarity is reversal (this bit is meaningful only chip operates at 10base-t) 11 resloved _speed ro to indicate the resolved speed mode 0: 10base-t 1: 100base-tx/fx 10 resloved _duplex ro to indicate the resolved duplex mode 0: half duplex 1: full duplex 9 mdi/mdix ro to indicate either at mdi or mdix state 0: mdi (not crossover) 1: mdix(crossover) 8..0 nway_debug _out ro nway debug output
ip100a lf preliminary data sheet 34/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.1.1 0 sca settings class............................. phy registers access method ............ . accessed through phyctrl register register address .......... 0x22 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 15 sca_mode r/w 1=set to sca mode. 0=default. 14 sca_chsel r/w 1= test mdix channel. 0= test mdi channel 13..11 reseverd n/a reseve for future use 10 sca_tx_pulse r/w 1= send a pulse for each write operation 0= do nothing 9..8 sca_phase r/w 00= phase do not increment 01= phase increment by 1 for each write operation 11= phase decrement by 1 for each write operation 10= reserved 7..0 sca_capture_len r/w adc outputs capture ti me after sending a pulse. the value must be greater than 0 for a capture event
ip100a lf preliminary data sheet 11. 2 dma data structures a tfd is used to move data destined for transmissi on onto an ethernet network, from the host system memory to the transmit fifo within the ip100a lf. a tfd is 16 to 512 bytes in length, and it?s location in host system memory is indicated by t he value in the txdmalistptr register. a rfd is used to move data obtained from an etherne t network, from the receive fifo within the ip100a lf to the host system memory. a rfd is 16 to 512 bytes in length, and it?s location in host system memory is indicated by the value in the rxdmalis tptr register. there are two formats for an rfd, differentiated by the impliedbufferenable bit of the rxframestatus field. figure 11 shows the two dma data structures. host system memory txdmanextptr txframecontrol txdmafragaddr0 txdmafraglen0 txdmafragaddr1 txdmafraglen1 txdmafragaddrn txdmafraglenn tfd host system memory rxdmanextptr rxframestatus rxdmafragaddr0 rxdmafraglen0 rxdmafragaddr1 rxdmafraglen1 rxdmafragaddrn rxdmafraglenn rfd offset from tfd start 0x00 0x04 0x08 0x0c 0x10 0x14 0x08+n*0x08 0x0c+n*0x08 offset from rfd start 0x00 0x04 0x08 0x0c 0x10 0x14 0x08+n*0x08 0x0c+n*0x08 figure 11: tfd and rfd dma data structures 11.2.1 rxdmafragaddr class............................. dma data structures, rfd base address ............... start of rfd address offset .............. 0x08+n*0x08 fo r nth fragment (w here n=0,1,...63) access mode ....... ......... read/write width ............................ 32 bits bit bit name bit description 31..0 rxdmafragaddr receive dma fragment a ddress. the rxdmafragaddr contains the physical address of a contiguous bl ock of system memory to which receive data is to be transferred by receive dma. a fragment can start on any byte boundary. march. 30, 2007 35/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 36/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.2. 2 rxdmafraglen class............................. dma data structures, rfd base address ............... start of rfd address offset .............. 0x0c+n*0x08 for nth fragment (w here n=0,1,...63) access mode ....... ......... read/write width ............................ 32 bits the rxdmafraglen contains fragment length and control information for the block of data pointed to by the corresponding rxdmafragaddr. bit bit name bit description 12..0 fraglen fragment length. the length of the contiguous block of data pointed to by the previous rxdmafragaddr. 30..13 reserved reserved for future use. 31 rxdmalastfrag set by the host system to indicate the last fragment of the receive frame. 11.2.3 rxdmanextptr class............................. dma data structures, rfd base address ............... start of rfd address offset .............. 0x00 access mode ....... ......... read/write width ............................ 32 bits bit bit name bit description 31..0 rxdmanextptr receive dma next poin ter. rxdmanextptr co ntains the physical address of the next rfd in the receiv e dma list. for the last rfd in the receive dma list, rxdmanextptr mu st be 0x00000000. rfds must be aligned on 8-byte physical address boundaries. 11.2.4 rxframestatus class............................. dma data structures, rfd base address ............... start of rfd address offset .............. 0x04 access mode ....... ......... read/write width ............................ 32 bits at the end of a receive dma transfer, the ip100a lf writes the value of the rxdmastatus register to rxframestatus. bit bit name bit description 12..0 rxdmaframelen receive dma frame length. rxdmaframelen indicates the true frame length, except in the case where the frame is larger than the total number of bytes specified in all of the fraglen subfields of the rxdmafraglen rfd field in which case, the rxdmaoverflow bit will be set. 13 reserved reserved for future use.
ip100a lf preliminary data sheet 37/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name bit description 14 rxframeerror receive frame error. rxframeerror indicates that an error occurred during receipt of the frame. the host system should examine rxfifooverrun, rxrunt frame, rxalignmenterror, rxfcserror, and rxoversizedframe to determine t he type of error(s). rxframeerror is undefined until rxdmacomplete is a logic 1. 15 rxdmacomplete receive dma complete. rx dmacomplete indicates the frame transfer from the ip100a lf to the host system is complete. 16 rxfifooverrun receive fi fo overrun. rxfifooverr un indicates the data was not removed from the receive fifo fast enough to keep up with the rate data was entering the receive fifo from the media. bytes may be missing from the frame at one or more unpredictable locations within the frame. rxfifooverrun is undefined until rxdmacomplete is a logic 1. 17 rxruntframe received runt frame. rxrunt frame indicates the received frame was a runt (less than 60 bytes in length, me asured from the da field to the end of the data field). rxruntframe is undefined until rxdmacomplete is a logic 1. 18 rxalignmenterror receive alignm ent error. rxruntframe indica tes that the received frame had an alignment error. rxalignmenterror is undefined until rxdmacomplete is a logic 1. 19 rxfcserror receive frame check sequenc e error. rxfcserror indicates a fcs checksum error on the frame dat a. rxfcserror is undefined until rxdmacomplete is a logic 1 20 rxoversizedframe receive oversized frame. rxoversizedframe indicates the frame size was equal to or greater than the value set in the maxframesize register. rxoversizedframe is undefined unt il rxdmacomplete is a logic 1. 22..21 reserved reserved for future use. 23 dribblebits dribble bits. dribblebits indicates that the frame had accompanying dribble bits. dribblebits is informational only, and does not indicate a frame error. 24 rxdmaoverflow receive dma overflow. rxdm aoverflow indicates that the rfd did not have sufficient buffer space to hold all of the frame data. for this condition, the ip100a lf transfers as much data as possible and discards the remainder of the frame. 27..25 reserved reserved for future use. 28 impliedbufferenable implied buffer enable. im pliedbufferenable enables a special receive dma mode. if impliedbufferenable is a logic 1 when the ip100a lf reads the rfd, the ip100a lf will assume th ere is one receive buffer of length 1528 bytes, starting immediately after receiveframestatus at (rfd address + 0x08). the host system sets impliedbufferenable when it prepares the rfd. the ip100a lf tests impliedbufferenable before receive dma for a frame begins at the same time it tests the rxdmacomplete bit. when the ip100a lf updates rxframestatus fi eld at the end of the receive dma operation (in order to set rxdmacomplete) the value written to impliedbufferenable is undefined. the host system cannot assume a certain value is left in impliedbufferenable after the rfd is used. therefore, the host system mu st write the desired value to impliedbufferenable every time after releasing a rfd to the ip100a lf. 31..29 reserved reserved for future use.
ip100a lf preliminary data sheet 38/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.2. 5 txdmafragaddr class............................. dma data structures, tfd base address ............... start of tfd address offset.............. 0x08+n*0x08 fo r nth fragment (where n=0,1,...63) access mode........ ........ read/write width ............................ 32 bits bit bit name bit description 31..0 txdmafragaddr transmit fragment addr ess. txdmafragaddr contains the physical address of a contiguous block of data to be transferred from the host system to the ip100a lf. a fragment can start on any byte boundary. 11.2.6 txdmafraglen class............................. dma data structures, tfd base address ............... start of tfd address offset .............. 0x0c+n*0x08 for nth fragment (w here n=0,1,...63) access mode ....... ......... read/write width ............................ 32 bits transmit fragment length (txdmafraglen) contains fragment length and control information for the block of data pointed to by the corresponding txdmafragaddr. bit bit name bit description 12..0 fraglen fragment length. fraglen is the length of the contiguous block of data pointed to by txdmafragaddr. the maximum fragment length is 8192 bytes. 30..13 reserved reserved for future use. 31 txdmafraglast transmit dma last fragment. txdmafraglast is set by the host system to indicate the last fragment of the transmit frame and that the ip100a lf should proceed to the next tfd. 11.2.7 txdmanextptr class............................. dma data structures, tfd base address ............... start of tfd address offset .............. 0x00 access mode ....... ......... read/write width ............................ 32 bits bit bit name bit description 31..0 txdmanextptr transmit dma next poin ter. txdmanextptr contains the physical address of the next tfd in the trans mit dma list. a value of zero for txdmanextptr accompanies the last frame of the list and it indicates there are no more tfd?s in the transmit dma list. all tfd?s must be aligned on a 8-byte physical address boundary.
ip100a lf preliminary data sheet 39/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.2. 8 txframecontrol class............................. dma data structures, tfd base address ............... start of tfd address offset .............. 0x04 access mode ....... ......... read/write width ............................ 32 bits txframecontrol contains frame control information fo r the transmit dma function and the transmit function. bit bit name bit description 1..0 wordalign word alignment. wordalign determine the boundary to which transmit frame lengths are rounded up in the transmit fifo, and transmitted onto the network medium. bit 1 bit 0 alignment 0 0 align to double word 1 0 align t o word x 1 alignment disabled when using word alignment, it is the responsibility of t he host system to recognize that any added bytes necessary to achieve the desired alignment may affect byte oriented func tions and fields (i.e. if the ethernet length/type field holds a frame length, this value is not updated to reflect any bytes added via word alignment). 9..2 frameid frame identification. frameid can be used as a frame id or sequence number and can be used by the host system (via the txstatus register) to determine frames which experienced errors. 12..10 reserved reserved for future use. 13 fcsappenddisable fcs append disable. if fcsa ppenddisable is a logic 1, the ip100a lf will not append the 4-byte fcs to the end of each transmit frame. in this case, the host system must supply t he frame?s fcs as part of the data transferred via transmit dma. an exc eption exists when a transmit under run occurs; in this case a guaranteed-bad fcs will be appended to the frame by the ip100a lf. when fcsappenddisable is a logic 0, the ip100a lf will compute and append fcs for each transmit frame. 14 reserved reserved for future use. 15 txindicate transmit indicate. if txindicate is a logic 1, the ip100a lf will issue a txcomplete interrupt when transmission of the frame completes. 16 txdmacomplete transmit dma complete. when txdmacomplete is a logic 1, the frame transfer by transmit dma is complete. the ip100a lf sets txdmacomplete to a logic 1 after completing transfer via transmit dma, all fragments specified in the tfd. 30..17 reserved reserved for future use. 31 txdmaindicate transmit dma indicate. if txdm aindicate is a logic 1, the ip100a lf will issue a txdmacomplete interrupt upon completion of transmit dma for this frame. the tfc is read twice by the ip100a lf; the first time to write the tfc to the transmit fifo before frame data transfer, and again after the transmit dma operation is complete to test txdmaindicate in order to determine whether to generate an interrupt. this dual read process allows the host system time to c hange txdmaindicate while the transmit dma transfer is in progress.
ip100a lf preliminary data sheet 11. 3 wake event data structures the first wake event data structure is the pseudo packet. a pseudo packet is a set of patterns loaded into the ip100a lf txfifo which specify bytes to be examined within received frames. a crc is calculated over these bytes and compared with a crc value supplied in the pseudo packet. if a match is found, the ip100a lf issues a wake event. the matc hing technique may result in false wake events being reported to the host system. each pseudo packet consists of one or more byte-offset/byte-count pairs (or pseudo patterns), a terminator symbol, and a 4-byte crc value. the byte offsets within the pseudo patterns indicate the number of received fram e bytes to be skipped in order to reach the next group of bytes to be included in the crc calculat ion. the byte-counts within the pseudo patterns indicate the number of bytes in the next group to be included in the crc calculation. the terminator indicates the end of the pseudo patterns for the pseudo pa cket. immediately following the terminator is a 4-byte crc. if there is another pseudo packe t, it will immediately follow the crc value. the second wake event data structure is the m agic packet. magic packets are uniquely formatted frames, which upon reception invoke a wake event by the ip100a lf. once the ip100a lf has been placed in magic packet mode and put to sleep, it sc ans all incoming frames addressed to it for a data sequence consisting of a synchronization stream fo llowed immediately by 16 consecutive repetitions of the station?s own 48-bit ethernet mac station address. the sequence can be located anywhere within the received frame. the pseudo packet and magic packet data structures are shown in figure 12 ip100a pseudo packet pseudopattern 1 terminator pseudopattern n pseudocrc 0x00 0x01 0x00+n+1 0x00+n 0x00+n-1 received packet 0x00 0x06 ethernet header magicsyncstream magicsequence ethernet crc magic packet tm figure 12 : wake event data struct ures, pseudo packet and magic packet 40/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17
ip100a lf preliminary data sheet 41/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.3. 1 magicsequence class............................. wake event data structures, magic packet base address ............... start of magic packet address offset .............. 0x06 access mode ....... ......... read only width ............................ 768 bits bit bit name bit description 767..0 magicsequence magic sequence. a sequence of 96 bytes, consisting of 16 consecutive, identical 6 bytes sequences, where each 6 byte sequence equals the station address of the station receiving the magic packet. 11.3.2 magicsyncstream class............................. wake event data structures, magic packet base address ............... start of magic packet address offset .............. 0x00 access mode ....... ......... read only width ............................ 48 bits bit bit name bit description 47..0 magicsyncstream magic packet sync stre am. a stream of 6 bytes with the value 0xff indicates the start of the magicsequence. 11.3.3 pseudocrc class..................... ........ wake event data structures, pseudo packet base address ............... start of pseudo packet address offset .............. 0x00+n+1 for n pseudopatterns access mode ................ write only width ............................ 32 bits the 32-bit crc as defined in t he ieee 802.3 ethernet st andard for the fcs, ta ken over the bytes (indicated by the pseudopattern values) of a received frame. bit bit name bit description 7..0 psuedocrcbyte0 the least significant byte of the pseudocrc. 15..8 psuedocrcbyte1 the second lest si gnificant byte of the pseudocrc. 23..16 psuedocrcbyte2 the second most significant byte of the pseudocrc. 31..24 psuedocrcbyte3 the most sign ificant byte of the pseudocrc.
ip100a lf preliminary data sheet 42/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.3. 4 pseudopattern class..................... ........ wake event data structures, pseudo packet base address ............... start of pseudo packet address offset .............. 0x00 thru 0x00+n-1 for nth pseudopattern access mode ................ write only width ............................ 8 bits bit bit name bit description 3..0 bytecount bytecount can take on a value of 0x0 to 0xe. a value of 0xf indicates an extended value. the extended value will occupy 8 bits and is contained in the next pseudopattern. if both the by teoffset and the bytecount values are 0xf, the next pseudopattern will be the extended byteoffset, and the pseudopattern after that will be the extended bytecount. 7..4 byteoffset byteoffset can take on a value of 0x0 to 0xe. a value of 0xf indicates an extended value. the extended value will occupy 8 bits and is contained in the next pseudopattern. if both the by teoffset and the bytecount values are 0xf, the next pseudopattern will be the extended byteoffset, and the pseudopattern after that will be the extended bytecount. 11.3.5 terminator class..................... ........ wake event data structures, pseudo packet base address ............... start of pseudo packet address offset .............. 0x00+n for n pseudopattern access mode ................ write only width ............................ 8 bits bit bit name bit description 7..0 terminator a value of 0x00 indicates the end of the pseudopattern.
ip100a lf preliminary data sheet 43/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11. 4 lan i/o registers the host interacts with the ip100a lf mainly through slave registers, which oc cupy 128 bytes in the host system?s i/o space, memory space, or both. generally, registers are referred to as ?i/o registers?, implying that the registers may in fact be mapped and accessed by the host sy stem in memory space. i/o registers must be accessed with instructions that are no larger than the bit-width of that register. the ip100a lf lan i/0 register layout is show in figure 13. byte 3 byte 2 byte 1 byte 0 addr offset hashtable[63..32] 0x64 hashtable[31..0] 0x60 phyctrl txreleasethresh receivemode 0x5c maxframesize stationaddress[47..32] 0x58 stationaddress[31..0] 0x54 macctrl1 macctrl0 0x50 intstatus intenable 0x4c intstatusack 0x48 txstatus wakeevent 0x44 0x40 0x3c fifoctrl 0x38 eepromctrl eepromdata 0x34 asicctrl 0x30 0x2c 0x28 0x24 0x20 0x1c 0x18 rxdmapollperiod rxdmaurgent- thresh rxdmaburst- thresh 0x14 rxdmalistptr 0x10 rxdmastatus 0x0c txdmapollperiod txdmaurgent- thresh txdmaburst- thresh 0x08 txdmalistptr 0x04 dmactrl 0x00 figure 13 : ip100a lf i/o register map
ip100a lf preliminary data sheet 44/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4. 1 asicctrl class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x30 default .................. .......0x00004000 (default values for le d speed, led, mode, physpeed10, physpeed100, phymedia are dependent on eeprom settings, and forcedconfig[1..0], forcedcon-fig[2] are dependent on ed signal pin states) width ............................ 32 bits asicctrl provides chip-specific, non-host-related settings. the contents of the least significant byte of asicctrl are read from eeprom at reset. bit bit name r/w bit description 0 ledflashspeed r the led flahing speed can be defined by this bit and could be set by eeprom only. 0: fast speed (5ms, 35ms). 1: low speed (20ms, 60ms). 1 led mode r the bit decide led mode, could be set by eeprom only. light emitting diode mode. ledmode is used to control the led signal pins functionality. when ledmode is a logic 0 the led signal pins operate in led mode 0. when ledmode is a logic 1 the led signal pins operate in led mode 1. note: when led mode 0 is set, the period of 1 cycle alternating between logic 1/0 is 100ms. the led on period is 20ms and off period is 80ms. when led mode 1 is set, the period of 1 cycle alternating between logic 1/0 is 200ms. the led on period is 40ms and off period is 160ms. led signal pin mode 0 mode 1 led_link this interface is not functioning under mode 0 continuous logic 0 when ethernet link is valid. led_10n continuous logic 0 when ethernet link is operate at 10mb/sec continuous logic 0 when ethernet link is operate at 10mb/sec led_100n continuous logic 0 when ethernet link is operate at 100mb/sec continuous logic 0 when ethernet link is operate at 100mb/sec led signal pin mode 0 mode 1 led_txn logic 0 indicates the frames are transmitting in progress, while logic 1 means no data is been sent. logic 0 indicates the link has established, while logic 1 indicates link is down. alternating logic 1 and 0 indicates the transmission or receiving is in progress. led_rxn logic 0 indicates the frames are been received. logic 1 indicates no frame is logic 0 indicates the link has established, while logic 1 indicates link is down. alternatin g lo g ic
ip100a lf preliminary data sheet 45/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description been received. 1 and 0 indicates the data receiving is in progress. led_dplxn logic 0 means the link is established based on full duplex mode, while logic 1 indicates half duplex mode. alternating logic 1 and 0 indicates collision has occurred. logic 0 means the link is established based on full duplex mode, while logic 1 indicates half duplex mode. 2 txlargeenable r/w transmit large frames enable. if txlargeenable is a logic 1, the ip100a lf may transmit frames which are larger in size than the ip100a lf transmit fifo. 3 rxlargeenable r/w receive large frames enable. if rxlargeenable is a logic 1, the ip100a lf may receive frames which are larger than the ip100a lf receive fifo. 4 expromdisable r/w expansion rom disa ble. if expromdisable is a logic 1, accesses to the on-adapter ex pansion rom are disabled and read to the expansion rom return 0x00000000 while writes to the expansion rom are ignored. 5 physpeed10 r physical device 10mbps capable. if physpeed10 is a logic 1, the ip100a lf phy is capable of operating at 10mbps. 6 physpeed100 r physical device 100mbps capable. if physpeed100 is a logic 1, the ip100a lf phy is capable of operating at 100mbps. 7 phymedia r physical device media type. if phymedia is a logic 0, copper media is in use. if phymedia is a l ogic 1, fiber media is in use. the combination of phymedia, physpeed100, and physpeed10 defines the capabilities of the phy. phy media phy speed100 phy speed10 phy capability 0 0 0 undefined 0 0 1 10base-t 0 1 0 100base-t 0 1 1 100base-t or 10base-t 1 0 0 undefined 1 0 1 10base-f 1 1 0 100base-f 1 1 1 100base-f or 10base-f 9..8 forcedconfig[1..0] r/w forced configuratio n. forcedconfig[1..0] is used to enable and select a forced configuration mode for the ip100a lf. forced configuration mode is targeted toward embedded applications which do not utilize an eeprom. in forced configuration mode, the ip100a lf is accessed via a pci bus without first performing pci configuration or loading parameters from an eeprom. the forcedconfig[1..0] bits 9 through 8 can also be set on reset using ed[4:3]. bit 9 bit 8 forced configuration mode 0 0 none 01 1
ip100a lf preliminary data sheet 46/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 0 1 1 1 x reserved in forced configuration mode 1, the ip100a lf is configured as follows: i/o base address = 0x200 i/o target cycles = enabled memory target cycles = disabled bus master cycles = enabled expansion rom cycles = disabled. 10 reserved n/a reserved for future use. 12..11 reserved n/a reserved for future use. 13 speedupmode r/w speed up mode. speedupmode is used for simulation purposes only. when speedupmode is a logic 1 ip100a lf operation is modified to decrease simulation time. speedupmode can also be set on reset using signal pin 20. 14 reserved n/a 15 reserved n/a reserved for future use. 16 globalreset w global reset. when globalreset is a logic 1, the ip100a lf resets the logic functions and registers specified by the dma, fifo, network, host, and autoinit bits (related to both the transmit and receive processes as applicable). the lan pci configuration registers are not affected by globalreset. globalreset is self-clearing. 17 rxreset w receive reset. when rxreset is a logic 1 the ip100a lf resets all of the receive logic function s and registers specified by the dma, fifo, and network bits. rx reset is self-clearing, and should not be used after initialization except to recover from receive errors such as a receive fifo over run. 18 txreset w transmit reset. when txreset is a logic 1 the ip100a lf resets all of the transmit logic function s and registers specified by the dma, fifo, and network bits. txreset is self clearing, and is required to be used after a transmit underrun error. 19 dma w dma reset. dma selects (when a logic 1) or excludes (when a logic 0) the ip100a lf dma f unctions and registers (see below) for/from reset based on the value of the globalreset, rxreset, and txreset bits. the dma bit is self-clearing. 20 fifo w fifo reset. fifo selects (when a logic 1) or excludes (when a logic 0) the ip100a lf fifo func tions and registers for/from reset based on the value of the globalreset, rxreset, and txreset bits. the fifo bit is self-clearing. 21 network w network reset. network se lects (when a logic 1) or excludes (when a logic 0) the ip100a lf network functions and registers for/from reset based on the value of the globalreset, rxreset, and txreset bits. the network bit is self-clearing. 23 autoinit w automatic initialization rese t. autoinit selects (when a logic 1) or excludes (when a logic 0) the ip 100a lf auto-initialization logic function for/from re-loading ip100a lf parameters from an eeprom based on the value of the globalreset bit. the autoinit bit is self-clearing.
ip100a lf preliminary data sheet 47/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 24 reserved n/a reserved for future use. 25 interruptrequest w interrupt request. when interruptrequest is a logic 1, the intrequested bit of the intstatus register is set to a logic 1. interruptrequest is self-clearing. 26 resetbusy r/w reset busy. when resetbusy is a logic 1 a reset process is in progress. after asserting a reset using the globalreset, rxreset, or txreset bits, the resetbusy bit must be polled (or periodically read) until it is a logic 0 indicati ng the reset operation is complete. 31..27 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 48/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.2 dmactrl class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x00 default ............. ............. 0x00000000 width ............................ 32 bits dmactrl controls some of the bus master function s in the receive dma and transmit dma logic, and contains status bits. dmac trl is cleared by a reset. bit bit name r/w bit description 0 rxdmahalted r receive dma halted. rxdmahalted is a logic 1 whenever receive dma is halted by setting rxdmahalt or an implicit halt due to fetching a rfd with rxdmacomplete in rxframestatus already a logic 1. rxdmahalted is cleared by setting rxdmaresume to a logic 1. 1 txdmacmplreq r transmit dma complete request. txdmacmplreq is equivalent to the txdmaindicate field in t he txframecontrol of the current tfd. 2 txdmahalted r transmit dma halted. txdmahalted is a logic 1whenever transmit dma is halted by setting txdmahalt. txdmahalted is cleared by setting txdmaresume to a logic 1. 3 rxdmacomplete r receive dma complete . rxdmacomplete is equivalent to the rxdmacomplete bit in the intsta tus register. rxdmacomplete is different from the rxdmacomplete bit in rxdmastatus. rxdmacomplete is latched once a frame receive dma transfer has completed. rxdmacomplete is cleared by acknowledging the rxdmacomplete bit in the intstatus register. 4 txdmacomplete r txdmacomplete. tx dmacomplete is the same as the txdmacomplete bit in intstatus register. txdmacomplete is cleared by acknowledging the txdmacomplete bit in the intstatus register. 7..5 reserved n/a reserved for future use. 8 rxdmahalt w receive dma halt. if rxdmah alt is a logic 1, the receive dma is halted. rxdmahalt is self-clearing and writing a 0 is ignored. see rxdmahalted to determine the running state of receive dma. 9 rxdmaresume w receive dma resume. if rxdmaresume is a logic 1, the receive dma is resumed. rxdmaresume is self-clearing and writing a 0 is ignored. see rxdmahalted to determine the running state of receive dma. 10 txdmahalt w transmit dma halt. if txdmahalt is a logic 1, the transmit dma is halted. txdmahalt is self-clearing and writing a 0 is ignored. see txdmahalted to determine the running state of transmit dma. 11 txdmaresume r/w transmit dma resume. if txdmaresume is a logic 1, the transmit dma is resumed. txdmaresume is self-clearing and writing a 0 is ignored. see txdm ahalted to determine the running state of transmit dma. 13..12 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 49/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 14 txdmainprog r transmit dma in progr ess. if txdmainprog is a logic 1, a transmit dma operation is in progress. txdmainprog is primarily used by the host system in an under run recovery routine. the host system waits for txdmainprog to be a logic 0 before setting the txreset bit of the asicctrl register to clear the under run condition. before checking txdmainprog, issue txdmahalt. 15 dmahaltbusy r dma halt busy. dmahaltbusy indicates that a dma halt operation (txdmahalt or rxdmahal t) is in progress and the host system should wait for dmahaltbusy to be cleared before performing other actions. 16 reserved n/a reserved for future use. 17 reserved n/a reserved for future use. 18 reserved n/a reserved for future use. 19 reserved n/a reserved for future use. 20 mwidisable r/w pci mwi command disable. if setting mwidisable is a logic 1, the ip100a lf will not use the memory write invalidate (mwi) pci command. 21 reserved n/a reserved for future use. 22 rxdmaoverrun- frame r/w receive dma overrun frame. if rxdmaoverrunframe is a logic 0, receive dma will discard receive overrun frames without transferring them to the host system. whenrxdmaoverrunframe is a logic 1, receive dma will transfer overrun frames to the host system. overrun frames are any frame whic h is received while the receive fifo is full. 29..23 reserved n/a reserved for future use. 30 targetabort r bus target abort. tar getabort is a logic 1 when the ip100a lf experiences a target abort sequence when operating as a bus master. targetabort indicates a fatal error, and must be cleared before further transmit dma or receive dma operation can proceed. targetabortt is cleared via the globalreset, and dma bits of the asicctrl register. 31 masterabort r bus master abort. mast erabort is a logic 1 when the ip100a lf experiences a master abort sequence when operating as a bus master. masterabort indicates a fatal error, and must be cleared before further transmit dma or receive dma operation can proceed. masterabortt is cleared via the globalreset, and dma bits of the asicctrl register.
ip100a lf preliminary data sheet 50/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4. 3 eepromctrl class............................. lan i/o regist ers, external interface control base address ............... ioba seaddress register value address offset .............. 0x36 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 5:0 eepromaddress r/w eeprom address. eepromaddr ess identify one of the 256, sixteen-bit words to be the ta rget for the readregister, writeregister or eraseregister commands. 7:6 eepromcommand r/w bits 7 and 6 are further defined to identify a sub-command based on the value of eepromopcode. the definition of bits 7 and 6 are valid when the eepromopcode in bits 9 and 8 equals 00. bit 7 bit 6 sub-command 0 0 writedisable 0 1 writeaii 1 0 eraseall 1 1 writeenable 9..8 eepromopcode r/w eeprom operation code. eepromop code specifies one of three individual commands and a single group of four sub-commands. if both bit 9 and bit 8 are logic zero, the opcode function will be based on the value in bit 6 and bit 7, otherwise bit 6 and bit 7 does not have any affect to these 2 bits. bit 9 bit 8 opcode command 0 0 don?t care 0 1 writeregister 1 0 readregister 1 1 don?t care note, after every writeregist er, eraseregister opcode, or writeall or eraseall subcommand, the ip100a lfwill automatically issue a writedi sable command to the eeprom. therefore, a writeenable command must be issued to the eeprom prior to every writeregister, eraser egister opcode, or writeall or eraseall subcommand. 10..11 reserved reserve for future use 12 93c46typesel r/w when the 93c46typsel is logic 1, ip100a lf accesses the 93c46 eeprom by normal address code. a nd when this bit is set to logic 0, ip100a lf read/write the 93c46 eeprom via special address code. this function is designed for special usage only. 13 eepromsel ro eeprom select. if this bit is logic 0, it means that ip100a lf is connected to 93c46 series eeprom. 14 reserved ro read back as 1. 15 eeprombusy r eeprom busy. eeprombusy is a logic 1 during the execution of eeprom commands. further comma nds should not be issued to eepromctrl nor should data be read from eeprom-data while eeprombusy is a logic 1.
ip100a lf preliminary data sheet 51/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4. 4 eepromdata class............................. lan i/o regist ers, external interface control base address ............... ioba seaddress register value address offset .............. 0x34 default ............. ............. 0x0000 width ............................ 16 bits eepromdata is a 16-bit data register for use with the adapter?s serial eeprom. data from the eeprom should be read by the host system from eepromdata register based on the state of the eeprombusy bit of the eepromctrl register. data to be written to the eeprom is writt en to eepromdata prior to issuing the write command to eepromctrl. bit bit name r/w bit description 15..0 eepromdata r/w eeprom da ta. data read from, or to be written to, the external eeprom. 11.4.5 fifoctrl class............................. lan i/o registers, fifo control base address ............... ioba seaddress register value address offset .............. 0x3a default ............. ............. 0x0000 width ............................ 16 bits fifoctrl provides various control and indications fo r the transmit fifo and the receive fifo diagnostic. bit bit name r/w bit description 0 ramtest mode r/ w ram tes t mode. i f ramt estmode is a logic 1, the fifo ram is in the test mode. 8..1 reserved n/a reserved for future use. 9 rxoverrunframe r/ w receive overrun frame. rxoverrunframe determines how the ip100a lf handles receive overrun frames. if rxoverrunframe is a logic 0, the ip100a lf discards all overrun frames. if rxoverrunframe is a logic 1, the ip100a lf will retain all overrun frames, so that they may be inspected by the host for diagnostic purposes. 10 reserved n/a reserved for future use. 11 rxfifofull r receive fifo full. if rxfifo full is a logic 1, the receive fifo is full. rxfifofull does not in itself indicate an overrun condition. however, if more data is received while rxfifofull is a logic 1, an overrun will occur. rxfifofull is cleared as soon as the receive fifo is no longer full. 13..12 reserved n/a reserved for future use. 14 transmitting r transmit indicator. transmitting is set to a logic 1 whenever a frame is being transmitted or during a transmit deferral). 15 receiving r receive indicator. receivin g is set to a logic 1 whenever a frame is being received. no action is expected on the part of the host based on the state of receiving.
ip100a lf preliminary data sheet 52/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4. 6 hashtable class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x66, 0x64, 0x62, 0x60 default ......... ................. 0x 0000000000000000 width ............................ 64 bits (accessible as 4, 16 bit words) the host system stores a 64-bit hash table in this register for selectively receiving multicast frames. setting the receivemulticasthash bit in receivem ode register enables the filtering mechanism. bit bit name r/w bit description 15..0 hashtableword0 r/w the least significant word of the hash table, corresponding to address 0x60. 31..16 hashtableword1 r/w the second least significant word of the hash table, corresponding to address 0x62. 47..32 hashtableword2 r/w the second most significant word of the hash table, corresponding to address 0x64. 63..48 hashtableword3 r/w the most significa nt word of the hash table, corresponding to address 0x66. the ip100a lf applies a cyclic-redundancy-check (the same crc used to calculate the frame data fcs) to the destination address of all incoming multicast fram es (with multicast bit set). the low-order 6 bits of the crc result are used as an addressing index into the hash table. the msb of hashtable[3] is the most significant bit, and the lsb of hashtable[0] is the least significant bit, addressed by the 6-bit index. if the hashtable bit addressed by the index is a logi c 1, the frame is accepted by the ip100a lf and transferred to higher layers. if t he addressed hash table bit is a logic 0, the frame is discarded. 11.4.7 intenable class............................. lan i/o registers, interrupt base address ............... ioba seaddress register value address offset.............. 0x4c default ............. ............. 0x0000 width ............................ 16 bits enables individual interrupts as specified in the ints tatus register. setting a bit in intenable will allow the specific source to generate an interrupt on the pci bu s. intenable is cleared by a read of intstatusack. bit bit name r/w bit description 0 reserved n/a reserved for future use. 1 enhosterror r/w enable host error inte rrupt. enables the hosterror interrupt. 2 entxcomplete r/w enable transmit comp lete interrupt. enables the txcomplete interrupt. 3 enmaccontrolframe r/w enable mac c ontrol frame interrupt. enables the maccontrolframe interrupt. 4 enrxcomplete r/w enable receive complete interrupt. enables the rxcomplete interrupt. 5 reserved r/w reserved for future use. 6 enintrequested r/w enable interrupt requ ested interrupt. enables the intrequested interrupt.
ip100a lf preliminary data sheet 53/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 7 enupdatestats r/w enable update stats in terrupt. enables the updatestats interrupt. 8 enlinkevent r/w enable link event inte rrupt. enables the linkevent interrupt. 9 entxdmacomplete r/w enable transmit dma complete interrupt. enables the txdmacomplete interrupt. 10 enrxdmacomplete r/w enable receive dma complete interrupt. enables the rxd-macomplete interrupt. 11 reserved n/a reserved for future use. 15..12 reserved n/a reserved for future use. 11.4.8 intstatus class?.......................... lan i/o registers, interrupt base address ?............ ioba seaddress register value address offset ?........... 0x4e default ?.......... ............. 0x0000 width ?......................... 16 bits intstatus indicates the source of interrupts and indications on the ip100a lf. all bits except interruptstatus are the interrupt causing sources for the ip100a lf. each interrupt source can be individually disabled using the intenable register. th e host system may acknowledge most interrupts by writing a logic 1 into the corresponding intstatus bit, which will cause the ip100a lf to clear the interrupt indication. bit bit name r/w bit description 0 interruptstatus r/w interrupt status. inte rruptstatus is a logic 1 when the ip100a lf is driving the bus interrupt signal (intan). interruptstatus is a logical or of all the interrupt causing sources after they have been filtered through the intenable register. 1 hosterror r/w host error interrupt. hosterror is a logic 1 when a catastrophic error related to the bus interface occurs. catastrophic bus interface errors include pci target abort and pci master abort. a hosterror interrupt requires a setting the globalreset and dma bits of the asicctrl register. 2 txcomplete r/w transmit complete. txcomplete is a logic 1 when a frame whose txindicate bit in the tfd?s txframecontrol field is a logic 1, has been successfully transmitted or fo r any frame that experiences a transmission error. a txcomplete interrupt requires wr iting to txstatus register to advance the status queue. 3 maccontrolframe r/w mac control frame received interrupt. maccontrolframe is a logic 1 when a mac control frame has been received by the ip100a lf. 4 rxcomplete r/w receive complete interrupt. rxcomplete is a logic 1 when one or more entire frames have been received into the receive fifo. rxcomplete is automatically acknowledged by the receive dma logic as it transfers frames. 5 reserved r/w reserved for future use.
ip100a lf preliminary data sheet 54/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 6 intrequested r/w interrupt requested interrupt. intrequested is a logic 1 after the host system requests an interrupt by setting interruptrequest bit of the asicctrl register. 7 updatestats r/w update statistics interr upt. updatestats is a logic 1 to indicate that one or more of the statisti cs registers is nearing an overflow condition (typically half of its maximum value). the host system should respond to an updatestats interrupt by reading all of the statistic registers, thereby acknowledging and clearing updatestats bit. 8 linkevent r/w link event interrupt. linkev ent is a logic 1 to indicate a change in the state of the ethernet link. 9 txdmacomplete r/w transmit dma complete interrupt. txdmacomplete is a logic 1 to indicate that a transmit dma operation has completed, and the frame?s corresponding tfd had the txdmacomplete bit in the txframecontrol field set to a logic 1. 10 rxdmacomplete r/w receive dma complete interrupt. rxdmacomplete is a logic 1 to indicate that a frame receive dma operation has completed. 11 reserved n/a reserved for future use. 15..12 reserved n/a reserved for future use. 11.4.9 intstatusack class............................. lan i/o registers, interrupt base address ............... ioba seaddress register value address offset .............. 0x4a default ............. ............. 0x0000 width ............................ 16 bits intstatusack is another version of the intstatus regi ster, having the same bit definition as intstatus, but providing additional functionality to reduce the nu mber of i/o operations required to perform common tasks related to interrupt handling. in addition to re turning the intstatus value, when read intstatusack also acknowledges the txdmacomplete, rxdmac omplete, intrequested, maccontrolframe, and linkevent interrupt bits within the intstatus register (if they are set) , and clears the intenable register (preventing subsequent events from generating an interrupt). bit bit name r/w bit description 0 interruptstatus r see interruptst atus in the intstatus register. 1 hosterror r see hosterror in the intstatus register. 2 txcomplete r see txcomplete in the intstatus register. 3 maccontrolframe r see maccontrol frame in the intstatus register. 4 rxcomplete r see rxcomplete in the intstatus register. 5 reserved r reserved for future use. 6 intrequested r see intrequest ed in the intstatus register. 7 updatestats r see updatestats in the intstatus register. 8 linkevent r see linkevent in the intstatus register. 9 txdmacomplete r see txdmacompl ete in the intstatus register. 10 rxdmacomplete r see rxdmacompl ete in the intstatus register.
ip100a lf preliminary data sheet 55/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 11 reserved n/a reserved for future use. 15..12 reserved n/a reserved for future use. 11.4.10 macctrl0 class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x50 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 1..0 ifsselect r/w inter-frame spacing select. ifsselect indicates the minimum number of bit times between the end of one ethernet frame, and the beginning of another when the ip100a lf is deferring after a collision with the ip100a lf the last device to successfully acquire the network (in half duplex mode). by selecting a large value for ifsselect, the ip100a lf will beco me less ?aggressive? on the network and may defer more often (preventing the ip100a lf from ?capturing? the network). the performance of the ip100a lf may decrease as the ifsselect value is increased from the standard value. bit1 bit0 inter-frame spacing in bit times 0 0 96 (802.3 standard value, and default) 0 1 128 1 0 224 1 1 544 4..2 reserved n/a reserved for future use. 5 fullduplexenable r/w full duplex enable. setting fullduplexenable to a logic 1 configures the ip100a lf to function in a full duplex manner. when operating in full duplex, the ip100a lf disables transmitter deference to receive traffic, allowing simultaneous receive and transmit traffic. operation in fu ll duplex has the side-effect of disabling carriersenseerrors statistics collection, since full duplex operation requires carrier sense to be masked to the transmitter. txreset and rxreset bits in asicctrl must be set for changes offullduplexenable to take effect. 6 rcvlargeframes r/w receive large frames. rcvlargeframes determines the frame size at which the rxoversizedframe bit of the rxframestatus field is set for receive frames. when rcvlargeframes is a logic 0, minimum oversizedframe size is 1514 bytes. when rcvlargeframes is set, minimum oversizedframe size is 4491 bytes. (this value was the maximum fddi frame size of 4500 bytes, subtracting bytes for fields that have no ethernet equivalent.) the frame size at which an oversizedframe error will be flagged includes the destination and source addresses, the type/length field, and the fcs field. 7 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 56/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 8 flowcontrol- enable r/w flow control enable. if flowcontrolenable is a logic 0, the ip100a lf treats all incoming frames as data frames. if flowcontrolenable is a logic 1, flow control is enabled and the ip100a lf will act upon incoming flow control pause frames. if flowcontrolenable is a logic 1, fullduplexenable should also be set to a logic 1. 9 rcvfcs r/w receive fcs. if rcvfcs is a logic 1, the ip100a lf will include the receive frame?s fcs along with the frame data transferred to the host system. if rcvfcs is a logic 0, the ip100a lf will remove the fcs from the frame before transferring the frame to the host system. the state of rcvfcs does not affect the ip100a lf?s checking of the frame?s fc s and its posting of fcs errors. rcvfcs should only be changed w hen the receiver is disabled (via the rxdisable bit of the macc trl1 register) and after resetting the receive fifo (via the fifo bit of the asicctrl register). 10 fifoloopback r/w fifo loopback. if fifolo opback is a logic 1, the ip100a lf will enter fifo loopback mode and force data to loopback from the transmit fifo directly into the receive fifo. when using fifo loopback mode, it is the host system?s responsibility to ensure that proper interframe spacing is ensured. to accommodate proper interframe spacing, the host sy stem must not load more than one transmit frame into the transmit fi fo at a time while in fifo loopback mode. the txreset and rxreset bits of the asicctrl register must be set after changing the value of fifoloopback. 11 macloopback r/w mac loopback. if macloopba ck is a logic 1, the ip100a lf will enter mac loopback mode and force data to loopback from the mac transmit interface to the mac receive interface. the txreset and rxreset bits in asicctrl register must be set after changing the value of macloopback. 15..12 reserved n/a reserved for future use. note: external loopback is controlled by the phy. to utilize exte rnal loopback, the host system must enable a loopback mode within the phy using the mii management interface. for the true ?on-the-wire? loopback mode, use a loopback plug (connector), clear the fifol oopback, and macloopback and any phy loopback bits to zero, set the fullduplexenable bit to a logic 1, and enable the full duplex mode within the phy. 11.4.11 macctrl1 class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x52 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 0 collisiondetect r collision detect. collision detect provides a real-time indication of the state of the col signal within the ip100a lf. 1 carriersense r carrier sense. carriersens e provides a real-time indication of the state of the crs signal within ip100a lf.
ip100a lf preliminary data sheet 57/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 2 txinprog r transmit in progress. tx inprog provides a real-time indication that a frame is being transmitted. if txinprog is a logic 1, a frame transmission is in progress. txinpr og is used by the host system during under run recovery to delay before setting the issuing a txreset bit in the asicctrl register. 3 txerror r transmit error. if a trans mit under run occurs (indicated via the txunderrun bit of the txstatus r egister), txerror is a logic 1, indicating that the transmitter needs to be reset via the txreset bit in the asicctrl register. 4 reserved n/a reserved for future use. 5 statisticsenable w statistics enable. writi ng a logic 1 to statisticsenable will enable the ip100a lf?s statistic register s. the state (enabled/disabled) of the ip100a lf?s statisti c registers is shown via statisticsenabled. 6 statisticsdisable w statistics disable. writing a logic 1 to statisticsdisable will disable the ip100a lf?s statistic register s. the state (enabled/disabled) of the ip100a lf?s statisti c registers is shown via statisticsenabled. 7 statisticsenabled r statistics enabled. if st atisticsenabled is a logic 1, the ip100a lf?s statistic registers are enabled. 8 txenable w transmit enable. writing a logic 1 to txenable will enable the ip100a lf to transmit frames. the state (enabled/disabled) of the ip100a lf?s transmitter is shown via txenabled. 9 txdisable w transmit disable. writing a logic 1 to txdisable will disable the ip100a lf from transmitting fram es. the state (enabled/disabled) of the ip100a lf?s transmitter is shown via txenabled. 10 txenabled r transmit enabled. if txenabl ed is a logic 1, the ip100a lf?s transmitter is enabled. 11 rxenable w receive enable. writing a logic 1 to rxenable will enable the ip100a lf to receive frames. the state (enabled/disabled) of the ip100a lf?s receiver is shown via rxenabled. 12 rxdisable w receive disabl e. writing a logic 1 to rxdisable will disable the ip100a lf from receiving frames . the state (enabled/disabled) of the ip100a lf?s receiver is shown via rxenabled. 13 rxenabled r receive enabled. if rxe nabled is a logic 1, the ip100a lf?s receiver is enabled. 14 paused r paused. if paused is a lo gic 1, the ip100a lf has received a pause mac control frame and the ip100a lf has halted the transmitter for the duration indicated in the pause frame?s pause_time field. paused will beco me a logic 0 when the ip100a lf?s transmitter ends is pause operation. 15 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 58/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.1 2 maxframesize class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset.............. 0x5a default ................. ......... 0x1514 or 0x4491 based on the rcvlargeframes bit in the macctrl0 register width ............................ 16 bits bit bit name r/w bit description 15..0 maxframesize r/w maximum frame size. received frames with sizes equal to or larger than maxframesize will be flagged as oversize via the rxoversizedframe bit in rxdmastat us field of the frame?s rfd. 11.4.13 phyctrl class............................. lan i/o regist ers, external interface control base address ............... ioba seaddress register value address offset .............. 0x5e default .......................... 0x00 width ............................ 8 bits phyctrl contains control bits for the internal mii management interface. the mii management interface is used to access registers in the ip100a lf phy. the host system accesses the mii management interface by writing and reading bit patterns to the phyctrl register. bit bit name r/w bit description 0 mgmtclk r/w management clock. mgmtclk drives the management clock (mdc) signal to the phy. 1 mgmtdata r/w management data bit. mgmtdata is directly connected to the mdio signal connected to the phy. data can be written to or read from the phy by writing or read mgmtdata based on the value of mgmtdir. 2 mgmtdir r/w management data direction. if the mgmtdir is a logic 1, the value written to mgmtdata is driven onto the mdio signal connected to the phy. when mgmtdir is a logic 0, data driven onto mdio by the phy can be read from mgmtdata. 3 reserved n/a reserved for future use. 4 phyduplexpolarity r/w phy duplex polarity. if phyduplexpolarity is a logic 0, the duplex status signal between the phy and the mac is active low. 5 phyduplexstatus r phy duplex status. if phyduplexstatus is a logic 1, the phy is operating in full duplex mode. if phyduplexstatus is a logic 0, the phy is operating in half duplex mode. 6 physpeedstatus r phy speed status. physpeedstatus provides a real-time indication of the ip100a lf?s phy speed. if physpeedstatus is a logic 1, the ip100a lf?s phy is operating at 100mbps operation. if physpeedstatus is a logic 0, the ip100a lf?s phy is operating at 10mbps operation. 7 phylinkstatus r phy link status. phylinks tatus provides a real-time indication of the ip100a lf?s phy link state. if phylinkstatus is a logic 1, the ip100a lf?s phy link is up. if phylinkstatus is a logic 0, the ip100a lf?s phy link is down.
ip100a lf preliminary data sheet 59/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.1 4 receivemode class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x5c default .......................... 0x00 width ............................ 8 bits receivemode sets the receive filter of the ip100a lf. bit bit name r/w bit description 0 receiveunicast r/w receive unicast. if re ceiveunicast is a logic 1, the ip100a lf receives unicast frames (frames where the da field matches the 48-bit value in the stationaddress register. 1 receivemulticast r/w receive multicast. if re ceivemulticast is a logic 1, the ip100a lf receives all multicast frames, including broadcast frames. 2 receivebroadcast r/w receive broadcast. if receivebroadcast is a logic 1, the ip100a lf receives all broadcast frames. 3 receiveallframes r/w receive all frames. if receiveallframes is a logic 1, the ip100a lf receives all frames. 4 receivemulticast- hash r/w receive multicast hash. if receiv emulticasthash is a logic 1, the ip100a lf receives all which pass the hash filtering mechanism defined in the hashtable register.. 5 receiveipmulticast r/w receive ip multicast. if receiveipmulticast is a logic 1, the ip100a lf receives all multic ast ip datagrams, which are mapped into ethernet multicast frames with destination address of 01:00:5e:xx:xx:xx as defined in rfc 1112 and rfc 1700. the first 3 bytes require exact match, and the last 3 bytes are ignored. 7..6 reserved n/a reserved for future use. 11.4.15 rxdmaburstthresh class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x14 default .......................... 0x08 width ............................ 8 bits rxdmaburstthresh register sets the threshold for receive dma bus master re quests by the ip100a lf based upon the number of used bytes in the receive fifo, in units of 32 bytes. when the used space exceeds the threshold, the ip100a lf may make a re ceive dma request on the pci bus. however, if the used space exceeds the rxdmaframelen field in t he current rfd, the ip100a lf will make receive dma bus request regardless of whether the us ed space exceeds the rxdmaburstthresh or not. rxdmaburstthresh may be overridden by the urg ent request mechanism. see the pci bus master operation section for information about the relationship between rxdmaburstthresh and rxdmaurgentthresh. any value less than 0x08 is invalid and is interpreted as 0x08. bit bit name r/w bit description 7..0 rxdmaburstthresh r/w receive dma burst threshold. the rxdmaburstthresh is the of 32 byte words which must be present in the receive fifo prior to the assertion of a receive dma bus master request.
ip100a lf preliminary data sheet 60/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.1 6 rxdmalistptr class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x10 default ............. ............. 0x00000000 width ............................ 32 bits rxdmalistptr is the physical addre ss of the current receive dma fram e descriptor in the receive dma list. a value of 0x00000000 for rxdmalistptr indicate s that no more rfds are available to accept receive frames. rxdmalistptr only points to addresse s on 8-byte boundaries, so rfds must be aligned on 8-byte physical address boundaries. rxdmalistptr may be written directly by t he host system to point the ip100a lf to the head of a newly created receiv e dma list. rxdmalistptr is also updated by the ip100a lf as it processes rfds in the receive dma list. as the ip100a lf finishes processing a rfd, it loads rxdmalistptr with the value from the rxdman extptr field of the current rfd in order to move on to the next rfd in the receive dma list. if t he ip100a lf loads a value of 0x00000000 from the current rfd, the receive dma logic enters the idle st ate, waiting for a non-zero value to be written to rxdmalistptr. to avoid access conflicts between th e ip100a lf and the host sy stem, the host system must set the rxdmahalt bit in the dmactrl register before writing to rxdmalistptr. bit bit name r/w bit description 31..0 rxdmalistptr r/w receive dma list pointer. rxdmalistptr is the physical address, on a 8-byte boundary, of the current rfd in the receive dma list. 11.4.17 rxdmapollperiod class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x16 default .......................... 0x00 width ............................ 8 bits rxdmapollperiod determines the rate at which the current rfd?s rxdm acomplete bit of the rxframestatus field in the rfd is polled for a logic 0. polling is disabled when rxdmapollperiod is 0x00. rxdmapollperiod is specified in increments of 320 ns. the maximum value is 127 (or 40.64 us). bit bit name r/w bit description 6..0 rxdmapollperiod r/w receive dma poll period. rxdmapollperiod is the number of 320ns intervals between polls of the rxdmacomplete bit in the rxframestatus field of the current rfd. 7 reserved n/a reserved for future use. 11.4.18 rxdmastatus class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x0c default ............. ............. 0x00000000 width ............................ 32 bits rxdmastatus shows the stat us of various operations in the re ceive dma logic. host systems should read rxdmastatus only if the rxdmahalted bit in t he dmactrl register is a logic 1. otherwise the ip100a lf may change rfds between accesses to rxdmastatus. many bits of rxdmastatus are identical to corresponding bits of the rxframestatus field.
ip100a lf preliminary data sheet 61/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 12..0 rxdmaframelen r receive dma frame length.rxdmaframelen is similar to the rxdmaframelen bit of the rxfram estatus field, except that rxdmaframelen provides a real-time indication of the number of bytes transferred during a receive dma operation. 13 reserved n/a reserved for future use. 14 rxframeerror r see the rxframeerror bit of the rxframestatus field. 15 rxdmacomplete r see the rxdmacomplet e bit of the rxframestatus field. 16 rxfifooverrun r see the rxfifooverrun bit of t he rxframestatus field. 17 rxruntframe r see the rxruntframe bit of the rxframestatus field. 18 rxalignmenterror r see t he rxalignmenterror bit of the rxframestatus field. 19 rxfcserror r see the rxfcserror bi t of the rxframestatus field. 20 rxoversizedframe r see t he rxoversizedframe bit of the rxframestatus field. 22..21 reserved n/a reserved for future use. 23 dribblebits r see the dribblebits bit of the rxframestatus field. 24 rxdmaoverflow r see the rxdmaoverflo w bit of the rxframestatus field. 31..25 reserved n/a reserved for future use. 11.4.19 rxdmaurgentthresh class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x15 default .......................... 0x04 width ............................ 8 bits rxdmaurgentthresh sets a threshold at which the receive dma logic will make a urgent bus master request. a urgent receive dma request will have priority over all other requests on the ip100a lf. the urgent bus request is made when the free space in the receive fifo falls below the value in rxdmaurgentthresh. a receive dma urgent request is not subject to the rxdmaburstthresh constraint. when the receive fifo is close to overrun, burst effi ciency is sacrificed in favor of requesting the bus as quickly as possible. the value in rxdmaurgentthresh represents free space in the receive fifo in terms of 32-byte portions. bit bit name r/w bit description 4..0 rxdmaurgentthresh r/w receive dma urgent threshold. rxdmaurgentthresh is the minimum number of 32-byte words which must be available in the receive fifo to avoid a receive dma urgent request. 7..5 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 62/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.2 0 stationaddress class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x54, 0x56, 0x58 default ................. ......... 0x000000000000 width ............................ 48 bits (accessible as 3, 16 bit words) stationaddress is used to define the individual desti nation address that the ip100a lf will respond to when receiving frames. network addresses are gene rally specified in the fo rm of 01:23:45:67:89:ab, where the bytes are received left to right, and the bits wi thin each byte are received right to left (isb to msb). the actual transmitted and received bi ts are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. bit bit name r/w bit description 15..0 stationaddress- word0 r/w the least significant word of the station address, corresponding to address 0x54. 31..16 stationaddress- word1 r/w the second least significant word of the station address, corresponding to address 0x56. 47..32 stationaddress- word2 r/w the most significant word of the station address, corresponding to address 0x58. the address comparison logic will compare the first 16 received destination address bits against stationaddressword0, the second 16 received destination address bits against stationaddressword1, and the third 16 received destination address bits against stationaddressword2. the value set in stationaddress is not inserted into the source address field of frames transmitted by the ip100a lf. the source address field for every frame must be specified by the host system as part of the frame data contents. 11.4.21 txdmaburstthresh class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x08 default .......................... 0x08 width ............................ 8 bits txdmaburstthresh determines the threshold for when the ip100a lf makes transmit dma bus master requests, based upon the available space in t he transmit fifo. txdmaburstthresh represents free space in the transmit fifo in multiples of 32 byte s. when the free space exceeds the threshold, the ip100a lf may make a transmit dma request. howeve r, if the free space exceeds the current fraglen subfield of the txframecontrol field within the curr ent tfd, the ip100a lf will make transmit dma bus request regardless of whether the free sp ace exceeds the txdmaburstthresh or not. txdmaburstthresh may be overridden by the txdm aurgentthresh mechanism. see the pci bus master operation section for information about the relationship between txdmaburstthresh and txdmaurgentthresh. any value less than 0x08 is invalid and is interpreted as 0x08. bit bit name r/w bit description 4..0 txdmaburstthresh r/w transmit dma burs t threshold. the number of 32-byte words which must be available in the tr ansmit fifo prior to assertion of a transmit dma burst request. 7..5 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 63/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.2 2 txdmalistptr class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x04 default ............. ............. 0x00000000 width ............................ 32 bits txdmalistptr holds the physical addr ess of the current transmit dma fr ame descriptor in the transmit dma list. a value of zero in txdmalistptr is interp reted by the ip100a lf to mean that no more frames remain to be transferred by transmit dma. txdm alistptr can only point to addresses on 8-byte boundaries, so tfd?s must be aligned on 8-byte boundar ies. txdmalistptr may be written directly by the host system to point the ip100a lf at the head of a newly created transmit dma list. writes to txdmalistptr are ignored while the current value in tx dmalistptr is non-zero. to avoid access conflicts between the ip100a lf and the host system, the hos t system must set the txdmahalt bit of the dmactrl register to a logic 1 before writing to tx dmalistptr (unless the host system has specific knowledge that txdmalistptr contains zero). bit bit name r/w bit description 31..0 txdmalistptr r/w transmit dma list pointer. txdmalistptr holds the physical address, on a 8-byte boundary, of the current tfd in the transmit dma list. the host may examine the txdmalistptr to determine which frame(s) have been transferred by transmit dma. those frames in the transmit dma list before the current txdmalistptr have already been transferred by transmit dma. if the txdmalistptr is zero, then all the frames have been transmitted. 11.4.23 txdmapollperiod class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x0a default .......................... 0x00 width ............................ 8 bits txdmapollperiod determines the interval at which the current tfd is polled. if the current tfds, txdmanextptr field is 0x00000000, the txdmanextptr field is polled to determine when a new tfd is ready to be processed. polling is disabled when tx dmapollperiod is 0x00. txdmapollperiod represents a multiple of 320 ns time intervals. the maximum value is 127 (or 40.64 us). bit bit name r/w bit description 6..0 txdmapollperiod r/w transmit dma poll period. the number of 320ns intervals between polls of the current tfd?s txdmanextptr field. 7 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 64/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.2 4 txdmaurgentthresh class............................. lan i/o registers, dma base address ............... ioba seaddress register value address offset .............. 0x09 default .......................... 0x04 width ............................ 8 bits when the number of used bytes in the transmit fifo falls below the value in the txdmaurgentthresh, the transmit dma logic will make an urgent bus mast er request. an urgent transmit dma request will have priority over the receive dm a, unless it is also making an urgent request. a transmit dma urgent request is not subject to the txdmaburstthresh co nstraint. the relaxation of the txdmaburstthresh constraint for this condition is because the transmit fifo is close to under run, and burst efficiency is sacrificed to avoid fifo under run. txdmaurgentthresh represents data in the transmit fifo in multiples of 32 bytes. bit bit name r/w bit description 5..0 txdmaurgentthresh r/w transmit dma urgent threshold. the minimum number of 32-byte words which must be occupied in the transmit fifo to avoid assertion of a transmit dma urgent request. 7..6 reserved n/a reserved for future use. 11.4.25 txreleasethresh class............................. lan i/o registers, fifo control base address ............... ioba seaddress register value address offset .............. 0x5d default .......................... 0x08 width ............................ 8 bits txreleasethresh determines how much data of a fr ame must be transmitted before the transmit fifo space can be released for use by another frame. once the number of bytes equal to the value in txreleasethresh have been transmitted, that number of bytes are discarded from the transmit fifo. thereafter, bytes are discarded as they are transmitted to the network. a value of 0xff in txreleasethresh disables the release mechanism and transmit fifo fram e space is not released until the entire frame is transmitted. the txreleaseerror bit in the txstatus register indicates when a frame experiences a collision after its release threshold has been crossed, preventi ng mac from retry. when a release error occurs, the transmitter is disabled, and the frame?s id or sequence number is visible in txstatus. bit bit name r/w bit description 7..0 txreleasethresh r/w transmit release th reshold. the number of 16 byte words which must be transmitted before the space in the transmit fifo occupied by the transmitted data can be released. to avoid excessive release errors d ue to in-window collisions, txreleasethresh should be greater than or equal to 0x04.
ip100a lf preliminary data sheet 65/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.2 6 txstatus class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x46 default ............. ............. 0x0000 width ............................ 16 bits txstatus returns the status of frame transmis sion or transmission attempts. txstatus actually implements a queue of up to 31 transmit status bytes. a write of an arbitrary value to txstatus will advance the queue to the next transmit status byte. bit bit name r/w bit description 0 reserved n/a reserved for future use. 1 txreleaseerror r transmit release error. if txreleaseerror is a logic 1, a transmit release error occurred, meaning that the frame transmission experienced a collision after the front of the frame had already been released to the transmit fifo free space. see txreleasethresh register. 2 txstatusoverflow r transmit status overflow. if txreleaseerror is a logic 1, the txstatus stack is full and as a result the transmitter has been disabled. writing an arbitrary value to txstatus clears txreleaseerror but the transmitter must be re-enabled vi a the txenable bit of the macctrl1 register before transmissions may resume. 3 maxcollisions r maximum collisions. if maxcollisions is a logic 1, a frame was not successfully transmitted due to encountering 16 collisions. the txenable bit of the macctrl1 register is used to recover from this condition. the frame is discarded from the transmit fifo. 4 txunderrun r transmit underrun. if txunderrun is a logic 1 the frame experienced an under run during t he transmit process because the host system was unable to supply the frame data fast enough to keep up with the network data rate. an under run will halt the transmitter and the transmit fifo. the txreset bit of the a sicctrl register is used to recover from an under run condition. 5 reserved n/a reserved for future use. 6 txindicatereqd r transmit indicate reques ted. if txindicatereqd is a logic 1, the txindicate bit of the txframecon trol field for the corresponding tfd was set. 7 txcomplete r transmit complete. if txcomplete is a logic 0, then the txreleaseerror, txstatusoverfl ow, maxcollisions, txunderrun, and txindicatereqd bits are undefined. if the host chooses to poll txstatus while waiting for a frame transmission to complete, then txcomplete is used to determine that a frame transmission attempt has either experienced an error, or has completed successfully with the txindicate bit set in the txframecontrol field of the corresponding tfd. 15..8 txframeid r/w transmit frame identification. txframeid contains the value from the frameid subfield within t he txframecontrol field of tfd corresponding to the currently transmitting or most recently transmitted frame. host syst ems can use txframeid during transmit error recovery by scanning through the tfd?s in the transmit dma list, searching fo r a match between the txframeid value and a txframecontrol?s, frameid value in the tfd.
ip100a lf preliminary data sheet 66/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.4.2 7 wakeevent class............................. lan i/o registers, control and status base address ............... ioba seaddress register value address offset .............. 0x45 default .......................... 0x00 width ............................ 8 bits wakeevent contains enable bits to control which types of events can generate a wake event to the host system. wakeevent also contains status bits indica ting the specific wake events which have occurred. bit bit name r/w bit description 0 wakepktenable r/w wake packet enable. if wakepktenable is a logic 1, the ip100a lf may generate wake events via a pci interrupt due to wake packet reception. the pmeen bit in the powermgmtctrl register must be set in order for wakepktenable to be recognized. wakepktenable has no effect in power mode d0. 1 magicpktenable r/w magic packet enable. if magicpktenable is a logic 1, the ip100a lf may generate wake events via a pci interrupt due to magic packet reception. the pmeen bit in the powermgmtctrl register must be set in order for magicpktenable to be recognized. magicpktenable has no effect in power mode d0. 2 linkeventenable r/w link event enable. if linkeventenable is a logic 1, the ip100a lf may generate wake events via a pci interrupt due to a change in link status (cable connect or disconnect). the pmeen bit in the powermgmtctrl register must be set in order for linkeventenable to be recognized. linkeventenable has no effect in power mode d0. 3 wakepolarity r/w wake polarity. if wakepola rity is a logic 1, the pmen signal will be asserted high. if wakepolarity is a logic 0, the pmen signal will be asserted low. 4 wakepktevent r wake packet event. if wa kepktevent is a logic 1, a wake packet (which meets the reception criteria set by the host system) has been received. wakepktenable must be a logic 1 for wakepktevent to operate. wakepktevent is cleared following a read of the wakeevent register. 5 magicpktevent r magic pack et event. if magicpktevent is a logic 1, a magic packet packet has been received. magicpktenable must be a logic 1 for magicpktevent to oper ate. magicpktevent is cleared following a read of the wakeevent register. 6 linkevent r link event. if linkevent is a logic 1, a link status event has occurred. linkeventenable must be a logic 1 for linkevent to operate. linkevent is cleared following a read of the wakeevent register. 7 wakeonlanenable r/w wake on lan enable. if wakeonlanenable is a logic 1, the ip100a lf is in wakeonlan mode regardless of the power management register settings in the configuration space. wakeonlanenable is loaded from the wakeonlanenable bit of asicctrl field within the eeprom.
ip100a lf preliminary data sheet 67/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11. 5 statistic registers the statistic registers implement several counte rs defined in the ieee 802.3 standard. note reading a statistic register will also clear that register. the statistics gat hering must be enabled by setting the statisticsenable bit in macctrl1 for the statistics register s to count events. 11.5.1 broadcastframesreceivedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x7d default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 broadcastframes- receivedok r/w broadcast frames received ok is the count of the number of frames that are successfully re ceived with destination address equal to the broadcast address (0xffffffffffff). broadcastframesreceivedok does not include frames received with frames too long, fcs, length or alignment errors, or frames lost due to internal mac sublayer error (i.e.overrun). broadcastframesreceivedok will wrap around to zero after reaching 0xff. see ieee 802. 3 clause 30.3.1.1.22. an updatestats interrupt (updates tats bit within the intstatus register) will occur when broadcastframesreceivedok reaches a value of 0xc0. broadcastframesreceivedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of broadcastframesreceiv edok also clears the register. 11.5.2 broadcastframestransmittedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x7c default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 broadcastframes- transmittedok r/w broadcast frames transmitt ed is the count of the number of frames that are successfully tr ansmitted to the broadcast address (0xffffffffffff). frames transmitted to other multicast addresses are excluded from this statistic. broadcastframestransm ittedok will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.19. an updatestats interrupt (updates tats bit within the intstatus register) will occur when broadc astframestransmittedok reaches a value of 0xc0. broadcastframestransmittedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of broadcastframestransmittedok also clears the register.
ip100a lf preliminary data sheet 68/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5. 3 carriersenseerrors class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x74 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 3..0 carriersenseerrors r/w carrier sense erro rs counts the number of times that the carrier sense signal (crs) was de-asserted (a logic 0) during the transmission of a frame without co llision. the carrier sense signal is not monitored for the purpose of this statistic until after the preamble and start-of-frame delimit er fields of the ethernet frame have been transmitted. carriersenseerrors will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.13. an updatestats interrupt (updates tats bit within the intstatus register) will occur wh en carriersense errors reaches a value of 0xc0. carriersenseerrors is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of carriersenseerrors also clears the register. 7..4 reserved r/w reserved for future use. 11.5.4 framesabortedduetoxscolls class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x7b default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 framesaborted- duetoxscolls r/w frames aborted due to excess collisions counts the number of frames which are not transmitted successfully due to excessive collisions. framesabortedduetoxsc olls will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.11. an updatestats interrupt (updates tats bit within the intstatus register) will occur when framesabortedduetoxscolls reaches a value of 0xc0. framesabortedduet oxscolls is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of framesabortedduetoxsco lls also clears the register.
ip100a lf preliminary data sheet 69/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5. 5 frameslostrxerrors class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x79 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 frameslostrxerrors r/w frames lost due to receive errors is a count of the number of frames that should have been re ceived (the destination address matched the filter criteria) but experienced a receive fifo overrun error (the receive fifo does not have enough free space to store the received data). frameslostrxerrors only includes overruns that become apparent to the host system, and does not include frames that are completely ignored due to a completely full receive fifo at the beginning of frame reception. frameslostrxerrors will wrap ar ound to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.15. an updatestats interrupt (updates tats bit within the intstatus register) will occur when frameslo strxerrors reaches a value of 0xc0. frameslostrxerrors is enabl ed by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of frameslostrxerrors also clears the register. 11.5.6 framesreceivedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x72 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 7..0 framesreceivedok r/w frames received ok is the count of the number of frames that are successfully received. framesreceivedok does not include frames received with frames too long, fcs, length or alignment errors, or frames lost due to in ternal mac sublayer error (i.e. overrun). framesreceivedok w ill wrap around to zero after reaching 0xffff. see ieee 802.3 clause 30.3.1.1.5. an updatestats interrupt (updates tats bit within the intstatus register) will occur when frames receivedok reaches a value of 0xc0. framesreceivedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of framesreceivedok also clears the register.
ip100a lf preliminary data sheet 70/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5. 7 framestransmittedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset.............. 0x70 default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 7..0 framestransmitted- ok r/w frames transmitted ok is a co unt of the number of frames that are successfully transmitted. framestransmittedok will wrap around to zero after reaching 0xffff. see ieee 802.3 clause 30.3.1.1.2. an updatestats interrupt (updates tats bit within the intstatus register) will occur when frames transmittedok reaches a value of 0xc0. framestransmittedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of framestransmittedok also clears the register. 11.5.8 frameswithdeferredxmission class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset.............. 0x78 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 frameswithdeferred- xmission r/w frames with deferred transmit is a count of the number of frames that must delay their first attempt of transmission because the medium was busy. frames invo lved in any collisions are not counted by frameswithdeferredxmission. frameswithdeferred- xmission wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.9. an updatestats interrupt (updates tats bit within the intstatus register) will occur when frameswithdeferredxmission reaches a value of 0xc0. frameswithdeferredxmission is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of frameswithdeferredxmission also clears the register.
ip100a lf preliminary data sheet 71/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5. 9 frameswithexcessivedeferal class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x7a default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 frameswithexcessi vedeferal r/w frames with excessive deferr als counts the number of frames that deferred for an excessive peri od of time (exceeding the defer limit). frameswithexcessivedeferal is only incremented once per llc frame. frameswithexcessivedeferal will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.20. an updatestats interrupt (updates tats bit within the intstatus register) will occur when frameswithexcessivedeferal reaches a value of 0xc0. frameswithexcessivedeferal is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of frameswithexcessivedeferal also clears the register. 11.5.10 latecollisions class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x75 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 latecollisions r/w late collisions is a count of the number of times that a collision has been detected later than 1 slot time into the transmitted frame. latecollisions will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.10. an updatestats interrupt (updates tats bit within the intstatus register) will occur when latecolli sions reaches a value of 0xc0. latecollisions is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of latecollisions also clears the register.
ip100a lf preliminary data sheet 72/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5.1 1 multicastframesreceivedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x7f default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 multicastframes- receivedok r/w multicast frames received ok is the count of the number of frames that are successfully received to a group destination address other than the broadca st address (0xffffffffffff). multicastframesreceivedok does not include frames received with frames too long, fcs, length or alignment errors, or frames lost due to internal mac sublayer error (i.e. overrun). multicastframesreceivedok will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.21. an updatestats interrupt (updates tats bit within the intstatus register) will occur when multic astframesreceivedok reaches a value of 0xc0. multicastframesreceivedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of multicastframesreceivedok also clears the register. 11.5.12 multicastframestransmittedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x7e default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 multicastframes- transmittedok r/w multicast frames transmitted ok is a count of the number of frames that are successfully transmitted to a group destination address other than the broadca st address (0xffffffffffff). multicastframestransmittedok will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.18. an updatestats interrupt (updates tats bit within the intstatus register) will occur when multic astframestransmittedok reaches a value of 0xc0. multicastframestransmittedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of multicastframestransmittedok also clears the register.
ip100a lf preliminary data sheet 73/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5.1 3 multiplecollisionframes class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x76 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 multiplecollision- frames r/w multiple collision frames is a c ount of the number of frames that are involved in more than one collision and are subsequently transmitted successfully. multipleco llisionframes will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.4. an updatestats interrupt (updates tats bit within the intstatus register) will occur when multip lecollisionframes reaches a value of 0xc0. multiplecollisionframes is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of multiplecollisionframes also clears the register. 11.5.14 octetsreceivedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset .............. 0x68 default ............. ............. 0x00000000 width ............................ 32 bits (accessible as 2, 16 bit words) bit bit name r/w bit description 19..0 octetsreceivedok r/w octets received ok is the count of the number of data and padding octets in frames that are successfully received. octetsreceivedok does not include frames received with frames too long, fcs, length or alignment errors, or frames lost due to internal mac sublayer error (i.e . overrun). octetsreceivedok will wrap around to zero after reaching 0xffffffff. see ieee 802.3 clause 30.3.1.1.14. an updatestats interrupt (updates tats bit within the intstatus register) will occur when octets receivedok reaches a value of 0xc0. octetsreceivedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of octetsreceivedok also clears the register. 31..20 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 74/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.5.1 5 octetstransmittedok class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset.............. 0x6c default ............. ............. 0x00000000 width ............................ 32 bits (accessible as 2, 16 bit words) bit bit name r/w bit description 19..0 octetstransmitted- ok r/w octets transmitted ok is a count of data and padding octets of frames successfully transmitte cm d. octetstransmittedok will wrap around to zero after reaching 0xffffffff. see ieee 802.3 clause 30.3.1.1.8. an updatestats interrupt (updates tats bit within the intstatus register) will occur when octetstr ansmittedok reaches a value of 0xc0. octetstransmittedok is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of octetstransmittedok also clears the register. 31..20 reserved n/a reserved for future use. 11.5.16 singlecollisionframes class............................. lan i/o registers, statistics base address ............... ioba seaddress register value address offset.............. 0x77 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 single collision frames r/w single collision frames is a count of the number of frames that are involved in a single collision, and are subsequently transmitted successfully. singlec ollisionframes will wrap around to zero after reaching 0xff. see ieee 802.3 clause 30.3.1.1.3. an updatestats interrupt (updates tats bit within the intstatus register) will occur when singlec ollisionframes reaches a value of 0xc0. singlecollisionframes is enabled by writing a logic 1 to the statisticsenable bit in the macctrl1 register. a read of singlecollisionframes also clears the register.
ip100a lf preliminary data sheet 75/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11. 6 lan pci configuration registers pci based systems use a slot-specific block of configuration registers to perform configuration of devices on the pci bus. the configuration registers are accessed with pci configuration cycles. each pci bus device is required to decode 256 bytes of configuration registers. of these, the first 64 bytes are pre-defined by the pci specification. the remaining registers may be used as needed for pci device-specific configuration registers. in pci configuration cycles, the host system provides a slot-specific decode signal (idsel) which informs the pc i device that a configurati on cycle is in progress. the pci device responds by asserting devseln, and decoding the specific configuration register from the address bus and the byte enable si gnals. see the pci expansion rom specification for information on generating configuration cycles from driver software. figure 14 shows the pci configuration registers im plemented by ip100a lf. all locations within the 256-byte configuration space that are not shown in the table, are not implemented and return zero when read. byte 3 byte 2 byte 1 byte 0 addr offset data powermgmtctrl 0x54 powermgmtcap nextitemptr capld 0x50 0x4c 0x48 0x44 0x40 maxlat mingnt interruptpin interruptline 0x3c 0x38 capptr 0x34 exprombaseaddress 0x30 subsystemld subsystemvendorld 0x2c cispointer 0x28 0x24 0x20 0x1c 0x18 membaseaddress 0x14 iobaseaddress 0x10 headertype latencytimer cachelinesize 0x0c classcode revisionld 0x08 configstatus configcommand 0x04 deviceld vendorld 0x00 figure 14 : ip100a lf pci register layout
ip100a lf preliminary data sheet 76/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6. 1 cachelinesize class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x0c default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 cachelinesize r/w cache line size. the sy stem bios writes the system?s cache line size into cachelinesize. the host system uses cachelinesize to optimize pci bus master operati on (choosing the best memory command, etc.). the value in cachelinesize represents the number of double words in a cache. cachelinesize values must be a power of two, from 0x04 to 0x80 (giving a range of 16 to 512 bytes). cachelinesize values which are not a power of two, between 4 and 128 are interpreted as 0x00. 11.6.2 capid class..................... ........ lan pci configuration registers, power management base address ............... pci devic e configuration header start address offset .............. 0x50 default .......................... 0x01 width ............................ 8 bits bit bit name r/w bit description 7..0 capid r capabilities id. capid in dicates the type of the capability data structure for the ip100a lf. capi d is set to the value 0x01 to indicate a pci power management structure. 11.6.3 capptr class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x34 default .......................... 0x50 width ............................ 8 bits bit bit name r/w bit description 7..0 capptr r capabilities pointer. capp tr indicates the beginning of a chain of registers which describe enhanced functions. capptr register returns 0x50, which is the address of the first in a series of power management registers.
ip100a lf preliminary data sheet 77/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6. 4 cispointer class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset.............. 0x28 default value ... ............. 0x00000802 width ............................ 32 bits cispointer identifies the location of the card informat ion structure (cis). cispointer contains the offset of cis in memory space. cispointer value is hard wired and can not be changed. although the cis is in memory, it is physically located in the eeprom. be cause the eeprom access is so slow, the pci target will issue a retry for each new access. bit bit name r/w bit description 2..0 addressspace- indicator r address space indicator. addr essspaceindicator specifies the base address within the space indicated. the addressspaceoffset is added to addressspaceindicator to identify the start of the cis. t he addressspaceindicator value is 0x2, indicating the ip100a lf only supports cis access in the memory pointed to by the pci base address register 1. 27..3 addressspaceoffset r address space offset. addressspaceoffset is the offset from the base address specified by the pci base address register 1. the ip100a lf supports cis in memory space. 31..28 romimagenumber r rom image number. romimagenumber is 0x0 indicating the ip100a lf does not support ci s access in the expansion rom. 11.6.5 classcode class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset.............. 0x09 default ............. ............. 0x020000 width ............................ 24 bits bit bit name r/w bit description 23..0 classcode r class code. classcode i dentifies the general function of the pci device. a value of 0x020000 indicates an ethernet network controller.
ip100a lf preliminary data sheet 78/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6. 6 configcommand class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x04 default ............. ............. 0x0000 width ............................ 16 bits configcommand provides control over the adapter?s ability to generate and respond to pci cycles. when a zero is written to configcommand, the ip100a lf is logically disconnected from the pci bus, except for configuration cycles. bit bit name r/w bit description 0 iospace r/w i/o space. when iospace is a logic the ip100a lf can respond to i/o space accesses (if the ip100a lf is in the d0 power state). 1 memoryspace r/w memory space. when memoryspace, and the addressdecodeenable bit in the exprombaseaddress register are both a logic 1, and if the ip100a lf is in the d0 power state, the ip100a lf is able to decode accesses to an expansion rom (if present). 2 busmaster r/w bus master. when busmaster is a logic 1 the ip100a lf is able to initiate bus master cycles (if the adapter is in the d0 power state). note: if the ip100a lf is initialized to pci-x mode, busmaster is ignored when initiating split completions. 3 reserved n/a reserved for future use. 4 mwlenable r/w memory write and invalidat e enable. when mwlenable is a logic 1 the ip100a lf is permitted to use the mwi command. 5 reserved n/a reserved for future use. 6 parityerrorresponse r/w parity error response. when parityerrorresponse is a logic 1 the ip100a lf responds to parity errors as defined within the pci specification. when parityerrorr esponse is a logic 0, the ip100a lf ignores parity errors. 7 reserved n/a reserved for future use. 8 serrenable r/w system error enable. wh en serrenable is a logic 1, the serrn signal is allowed to transition as appropriate. when serrenable is a logic 0, the serrn signal is a continuous logic 0. 15..9 reserved n/a reserved for future use.
ip100a lf preliminary data sheet 79/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6. 7 configstatus class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset.............. 0x06 default ............. ............. 0x0210 width ............................ 16 bits configstatus is used to record stat us information for pci bus events. read/write bits inconfigstatus can only be reset, not set, by writing to this register. bits are reset by writing a one to the corresponding bit. bit bit name r/w bit description 3..0 reserved n/a reserved for future use. 4 capabilities r capabilities. capabilities is a logic 1 to indicate a set of extended capabilities registers exists for the ip100a lf. the capptr register indicates the first address location of the extended capabilities register set. 6..5 reserved n/a reserved for future use. 7 fastbacktoback r fast back to back. when fastbacktoback is a logic 1 the ip100a lf when operating as a target, supports fast back-to-back transactions as defined by the criteria in the section 3.4.2 of the pci specification. 8 dataparityreported r/w master data parity error. when dataparityreported is a logic 1, the ip100a lf when operating as a master, has detected the perrn signal asserted, and the parityerrorresponse bit in the configcommand register as a logic 1. 10..9 devseltiming r device select timing. devseltiming is used to encode the slowest time with which the ip100a lf asserts the devseln signal. a value of 0x1 for devseltiming indicates support for ?medium? speed devseln assertion. 11 signaledtargetabort r/w si gnaled target abort. the ip100a lf sets signaledtargetabort to a logic 1 when the ip100a lf te rminates a bus transaction with target-abort. 12 receivedtargetabort r/w received target abort. the ip100a lf sets receivedtargetabort to a logic 1 when, operating as a bus master, a ip100a lf bus transaction is terminated with target-abort. 13 receivedmasterabort r/w received master abort. the ip100a lf sets receivedmasterabort to a logic 1 when, operating as a bus master, a ip100a lf bus transaction is terminated with master-abort. 14 signaledsystemerror r/w signaled system error. when signaledsystemerror is a logic 1, the ip100a lf asserts the serrn signal. 15 detectedparityerror r/w detected parity error. when detectedparityerror is a logic 1 the ip100a lf has detected a parity error, regardless of whether parity error handling is enabled.
ip100a lf preliminary data sheet 80/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6. 8 data class..................... ........ lan pci configuration registers, power management base address ............... pci devic e configuration header start address offset .............. 0x57 default value ................ 0x00 width ............................ 8 bits data reports the power consumption of the ip100a lf . the values of dataselect and datascale in the powermgmtctrl register are used to interpret the value of data. bit bit name r/w bit description 7..0 data r data. data reports power consumption and dissipation of the ip100a lf at worst-case conditions. to properly interpret the value read from data, it must be sc aled by the factor indicated in the datascale field of the powermgmtctrl register. the value of data depends on the value of the dataselect field of the powermgmtctrl register. data is loaded from the data field in the eeprom during a autoinit reset. dataselect data 0x0 1 * datascale watts d0 power consumption 0x1 1 * datascale watts d1 power consumption 0x2 1 * datascale watts d2 power consumption 0x3 1 * datascale watts d3 power consumption 0x4 1 * datascale watts d4 power dissipated 0x5 1 * datascale watts d5 power dissipated 0x6 1 * datascale watts d6 power dissipated 0x7 1 * datascale watts d7 power dissipated 0x8 through 0xf 0x00 reserved. 11.6.9 deviceid class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x02 default value ................ 0x0200 width ............................ 16 bits bit bit name r/w bit description 15..0 deviceid r deviceid contains the 16-bit device id for the ip100a lf.
ip100a lf preliminary data sheet 81/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6.1 0 exprombaseaddress class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x30 default ............. ............. 0x00000000 width ............................ 32 bits exprombaseaddress allows the system to defi ne the base address for the adapter?s expansion rom. exprombaseaddress is disabled (read only with a value of 0x00000000) when the ip100a lf is in multi-function mode (see the reserved/multif unction bit in the asicctrl register). bit bit name r/w bit description 0 addressdecode- enable r/w address decode enable. if addressdecodeenable is a logic 0, the ip100a lf?s expansion rom is disabled. if addressdecodeenable is a logic 1, and the memoryspace bit in the configcommand register is a logic 1, the ip100a lf will respond to accesses to the expansion rom space. 14..1 reserved n/a reserved for future use. 31..15 rombaseaddress r/w rom base address. rombaseaddress contains the expansion rom base address, or the upper 16 bits (or 15 bits, depending on the state of the expromsize bit in the asicctrl register) of the expansion rom address range. if the expromsize bit in the asicctrl register is a logic 0, all 16 bits of rombaseaddress are valid . if the expromsize bit in the a sicctrl register is a logic 1, bits 31 through 16 of rombaseaddress are valid, with bit 15 ignored (set to a logic 0) during write operations. 11.6.11 headertype class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x0e default .......................... 0x00 (single function)/0x80 (multi-function) width ............................ 8 bits bit bit name r/w bit description 7..0 headertype r header type. if the reserved/multifunction bit in the asicctrl register is a logic 0, headertype is set to 0x00 identifying the ip100a lf as a single-function pci device and specifying the configuration register layout. if the reserved/multifunction bit in the asicctrl register is a logic 1, headertype is set to 0x80 identifying the ip100a lf as a multi-function pci device and spec ifying the configuration register layout.
ip100a lf preliminary data sheet 82/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6.1 2 interruptline class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x3c default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 interruptline r/w interrupt line. interrupt line specifies the interrupt level used by the ip100a lf. by setting interruptline the host system may configure the appropriate interrupt vector for its interrupt service routine. for 80x86 processor based host systems, interruptline corresponds to the irq number (0x00 through 0x0f), with the value 0xff corresponding to disabled interrupts. 11.6.13 interruptpin class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x3d default .......................... 0x01 width ............................ 8 bits bit bit name r/w bit description 7..0 interruptpin r interrupt pin. interruptpin indicates which pci interrupt signal the ip100a lf will utilize. the ip100a lf always utilizes the intan interrupt signal, corresponding to an interruptpin value of 0x01. 11.6.14 iobaseaddress class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x10 default ............. ............. 0x00000001 width ............................ 32 bits iobaseaddress is used to define the i/o base address for the ip100a lf. pci sy stems requires that the i/o base address be set as if the system used 32-bit i/o addressing. the upper 25 bits of iobaseaddress are read/write accessible, indicating that the ip100a lf requires 128 bytes of i/o space in the system i/o map. bit bit name r/w bit description 0 iobaseaddrind r i/o base address indicator. when iobaseaddrind is a logic 1, iobaseaddress contains the valid i/o base address for the ip100a lf. 6..1 reserved n/a reserved for future use. 31..7 iobaseaddress r/w i/o base address. iobaseaddress contains the 25 bit i/o base address value. the ip100a lf us es 128 bytes of i/o address space.
ip100a lf preliminary data sheet 83/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6.1 5 latencytimer class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x0d default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 2..0 reserved n/a reserved for future use. 7..3 latencytimer r/w latency timer. latency timer indicates, in increments of 8 bus clocks, the length of time which the ip100a lf may hold the pci bus in the presence of other bus requestors. whenever the ip100a lf asserts the framen signal, the latency timer is started. when the latency time r count expires, the ip100a lf must relinquish the bus as soon as its gntn signal has been deasserted. 11.6.16 maxlat class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x3f default .......................... 0x0a width ............................ 8 bits bit bit name r/w bit description 7..0 maxlat r maximum latency. maxlat specifies, in 250 ns increments, how often the ip100a lf requires bus access while operating as a bus master. bits 5 through 1 of the maxlat value are loaded from the configparm field within an eeprom during auto initialization of the ip100a lf. 11.6.17 membaseaddress class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x14 default ............. ............. 0x00000000 width ............................ 32 bits membaseaddress can be disabled via loading of the configparm field from an eeprom during auto-ini-tialization of the ip100a lf. bit bit name r/w bit description 0 membaseaddrind r memory base address indicator. when membaseaddrind is a logic 1, membaseaddrind cont ains the valid memory base address.
ip100a lf preliminary data sheet 84/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 2..1 memmaptype r memory map type. memmaptype defines how the host system maps the ip100a lf?s registers within the host system memory space. bit 2 of memmaptype is always a logic 0, while bit 1 is loaded from the lower1meg bit of the configparm field within an eeprom during auto initialization of the ip100a lf. bit 2 bit 1 register mapping 0 0 anywhere within a 32 bit address space 0 1 lower 1 megabyte of 32 bit address space 1 x undefined 6..3 reserved n/a reserved for future use. 31..7 membaseaddress r/w memory base addr ess. membaseaddress contains the 25 bit memory base address value. the ip100a lf uses 128 bytes of i/o space. 11.6.18 mingnt class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x3e default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 mingnt r minimum grant time. mi ngnt specifies, in 250 ns increments, how long a burst period the ip100a lf requires when operating as a bus master. bits 7 through 4 of the mingnt value are loaded from the configparm field within an eeprom during auto initialization of the ip100a lf. 11.6.19 nextitemptr class..................... ........ lan pci configuration registers, power management base address ............... pci devic e configuration header start address offset .............. 0x51 default .......................... 0x00 width ............................ 8 bits bit bit name r/w bit description 7..0 nextitemptr r next item pointer. ne xtitemptr indicates the next capability data structure in the capabilities list. when nextitemptr is set to the value 0x00, there are no further data structures.
ip100a lf preliminary data sheet 85/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6.2 0 powermgmtcap class..................... ........ lan pci configuration registers, power management base address ............... pci devic e configuration header start address offset .............. 0x52 default value ................ 0x7602 width ............................ 16 bits powermgmtcap provides information about the ip100a lf?s power management capabilities. several bits are loaded from the eeprom during auto-initialization. bit bit name r/w bit description 2..0 versi on r version. version is set to 0x2, indicating pci bus power management specification revision 1.1. 3 reserved n/a reserved for future use. 4 vaux r auxiliary voltage. if vaux is a logic 1, auxiliary power via the pci bus is required from the system to support pme in the d3cold state. if vaux is a logic 0, auxiliary power is supplied from elsewhere (i.e. not from the pci bus) to support pme in the d3cold state. 8..5 reserved n/a reserved for future use. 9 d1support r d1 power state support. when d1support is a logic 1, the ip100a lf supports the d1 powe r state. d1support is loaded from the configparm field of an eeprom during auto initialization of the ip100a lf. 10 d2support r d2 power state support. when d2support is a logic 1, the ip100a lf supports the d2 powe r state. d2support is loaded from the configparm field of an eeprom during auto initialization of the ip100a lf. 15..11 pmesupport r power management event support. pmesupport indicates the power states from which the ip100a lf is able to generate a power management event by asserting the pmen signal. each bit corresponds to a power state. a logic 1 in a particular bit position indicates that events can be gener ated from the indicated power state. bit 15 bit 14 bit 13 bit 12 bit 11 power management event may be generated from state x x x x 1 d0 x x x 1 x d1 x x 1 x x d2 x 1 x x x d3hot 1 x x x x d3cold pmesupport bit 11 and 14 are hard-wired to 0 and 1 respectively, while bits 12, 13, and 15 are loaded from the configparm field of an eeprom during auto initializ ation of the ip100a lf.
ip100a lf preliminary data sheet 86/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.6.2 1 powermgmtctrl class..................... ........ lan pci configuration registers, power management base address ............... pci devic e configuration header start address offset .............. 0x54 default value ................ 0x4000 width ............................ 16 bits powermgmtctrl allows control over the power state and the power management interrupts. bit bit name r/w bit description 1..0 powerstate r/w power st ate. powerstate indicates the current power state of the ip100a lf. if powerstate is set to a value other than 0x0, the ip100a lf will not respond to pci i/o or memory cycles, nor will the ip100a lf be able to generate pci bus master cycles. bit 1 bit 0 power state 0 0 d0 0 1 d1 1 0 d2 1 1 d3 7..2 reserved n/a reserved for future use. 8 pmeen r/w power management event e nable. when pmeen is a logic 1, the ip100a lf is allowed to report wake events on the pmen signal. the criteria for generating wake events is defined by the wakeevent register. pmeen is loaded from the configparm field of an eeprom during auto initialization of the ip100a lf. 12..9 dataselect r/w data select. dataselect is used to select which data is to be reported through the data register and datascale field. 14..13 datascale r data scale. datascale indicates the scaling factor to be used when interpreting the value of the data register. the interpretation of the scale values is defined as follows: datascale scale factor 0x0 unknown 0x1 0.1 0x2 0.01 0x3 0.001 15 pmestatus r/w power management event st atus. when pmestatus is a logic 1 a wake event has occurred. pmesta tus may be a logic 1 regardless of the value of pmeen. writing a logic 1 to pmestatus will set pmestatus to a logic 0. writing a logic 0 to pmestatus has no effect. 11.6. 22 revisionid class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x08 default ............. ............. depends on revision of ac tual device. see description below. width ............................ 8 bits
ip100a lf preliminary data sheet 87/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name r/w bit description 7..0 revisionid r revision id. revisionid contains the revision code for the ip100a lf. revisionid silicon revision 30 b0 11.6.23 subsystemid class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x2e default ............. ............. 0x0000 width ............................ 16 bits bit bit name r/w bit description 15..0 subsystemid r subsyste m id. subsystemid contains the value loaded from the configparm field within an eeprom during auto initialization of the ip100a lf. 11.6.24 subsystemvendorid class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x2c default .......................... eeprom value width ............................ 16 bits bit bit name r/w bit description 15..0 subsystemvendorid r subsystem vendor id . subsystemvendorid contains the value loaded from the configparm fi eld within an eeprom during auto initialization of the ip100a lf. 11.6.25 vendorid class............................. lan pci config uration registers, configuration base address ............... pci devic e configuration header start address offset .............. 0x00 default .......................... 0x13f0 width ............................ 16 bits bit bit name r/w bit description 15..0 vendorid r vendor id. vendorid contains the unique 16-bit manufacturer?s id as allocated by the pci special interest group. the manufacturer id is 0x13f0.
ip100a lf preliminary data sheet 88/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11. 7 eeprom data format figure 15 summarizes the layout of the eeprom. 16 bit word addr offset stationaddress 0x12 stationaddress 0x11 stationaddress 0x10 0x0f 0x0e 0x0d 0x0c 0x0b functionsctrl 0x0a : : : : subsystemld 0x03 subsystemvendorld 0x02 asicctrl 0x01 configparm 0x00 figure 15 : ip100a lf eeprom field layout 11.7.1 asicctrl class............................. eeprom data format base address ......... ...... 0x00, address written to eepromctrl register address offset .............. 0x01 access mode ....... ......... read only width ............................ 16 bits asicctrl supplies the value for the least significan t byte of the asicctrl register and the wakeevent register. bit bit name bit description 0 ledflashspeed this bit determines the flashing speed of the led. set to 0 will have led on and off ratio of 5 : 35 ms(fast) set to 1 will have led on and off ratio of 20 : 60 ms(slow) ledflashspeed corresponds to the ledflashspeed bit in the asicctrl register. 1 led mode 0: set led mode 0 1: set led mode 1 led mode corresponds to the led mode bit in the asicctrl register. 2 txlargeenable transmit large frames enable. txlargeenable corresponds to the txlargeenable bit in the asicctrl register. 3 rxlargeenable receive large frames e nable. rxlargeenable corresponds to the rxlargeenable bit in t he asicctrl register.
ip100a lf preliminary data sheet 89/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 bit bit name bit description 4 expromdisable expansion rom disable. expromdisable corresponds to the expromdisable bit in the asicctrl register. 5 physpeed10 physical layer device speed 10mbps. physpeed10 corresponds to the physpeed10 bit in the asicctrl register. 6 physpeed100 physical layer device speed 100mbps. physpeed100 corresponds to the physpeed100 bit in the asicctrl register. 7 phymedia physical layer device media. phymedia corresponds to the phymedia bit in the asicctrl register. 14..8 reserved reserved for future use. 15 wakeonlanenable wake on lan enable. wakeonlanenable corresponds to the wakeonlanenable bit in the wakeevent register. 11.7.2 configparm class............................. eeprom data format base address ......... ...... 0x00, address written to eepromctrl register address offset .............. 0x00 access mode ....... ......... read only width ............................ 16 bits bit bit name bit description 0 fastbacktoback fast back to back. fastbacktoback corresponds to the fastbacktoback bit in the configstatus register. 1 lower1meg lower 1 megabyte. lower1meg co rresponds to bit 1 of the memmaptype bit in the membaseaddress register. 2 disablemembase disable memory base address register. disablemembase does not correspond directly to any register accessible by the host system. if disablemembase is a logic 1 during au to initialization of the ip100a lf, the membaseaddress register will be disabled. when disabled, the value returned when the membaseaddress register is read is undefined. 3 d3coldpme d3 cold power management event. d3coldpme corresponds to the pmesupport bit in the powermgmtcap register. 4 d1support d1 power state support. d1support corresponds to the d1support bit in the powermgmtcap register. 5 d2support d2 power state support. d2support corresponds to the d2support bit in the powermgmtcap register. 6 pmeen power management event enable. pmeen corresponds to the pmeen bit in the powermgmtctrl register. 10..7 mingnt minimum grant. mingnt corresponds to bits 7 through 4 of the mingnt register. 15..11 maxlat maximum latency. maxlat corres ponds to bits 5 through 1 of the maxlat register.
ip100a lf preliminary data sheet 90/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.7. 3 functionsctrl class............................. eeprom data format base address ......... ...... 0x00, address written to eepromctrl register address offset .............. 0x0a access mode ....... ......... read only width ............................ 16 bits bit bit name bit description 0 ldps enable link-down-power-s aving mode. set this bit to 1 will reduce the power usage of ip100a lf if the link bet ween ip100a lf and another terminal has terminated. 1 auto-cross-over enable enable auto cross function. at logic 1, ip100a lf will be able to use both crossover utp wire and non-crossover utp wire. 2 reserved reserved for future use. default setting as 0 3 last-gasp control enable last gasp function. at logic 1, ip100a lf will activate last gasp function, and ip100a lf will be able to send last gasp frames. 6..4 last-gasp repeat time these 3 bits will decide the number of last gasp packets to send. since there are 3 bits controlling the amount of packet sent, thus the maximum number of packets is 8 frames. 7 last-gasp op code decision of the last gasp op code. this bit determines the op code within the last gasp frames. at 0: last-gasp packet send op code is 0001 at 1: last-gasp packet send op code is 0100 15..8 dsp settings setting to phy dsp 11.7.4 stationaddress class............................. eeprom data format base address ......... ...... 0x00, address written to eepromctrl register address offset .............. 0x10, 0x11, 0x12 access mode ....... ......... read only width ............................ 48 bits bit bit name bit description 15..0 stationaddress0 station address 0. stat ionaddress0 (offset 0x10) corresponds to the stationaddressword0 field of the stationaddress register. 31..16 stationaddress1 station a ddress 1. stationaddress1 (offs et 0x11) corresponds to the stationaddressword1 field of the stationaddress register. 47..32 stationaddress2 station a ddress 2. stationaddress2 (offs et 0x12) corresponds to the stationaddressword2 field of the stationaddress register.
ip100a lf preliminary data sheet 91/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 11.7. 5 subsystemid class............................. eeprom data format base address ......... ...... 0x00, address written to eepromctrl register address offset .............. 0x03 access mode ....... ......... read only width ............................ 16 bits bit bit name bit description 15..0 subsystemid subsystem id. subsystemid corresponds to the subsystemid register. 11.7.6 subsystemvendorid class............................. eeprom data format base address ......... ...... 0x00, address written to eepromctrl register address offset .............. 0x02 access mode ....... ......... read only width ............................ 16 bits bit bit name bit description 15..0 subsystemvendorid subsystem vendor id. subsystemvendorid corresponds to the subsystemvendorid register.
ip100a lf preliminary data sheet 92/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 12 signal requirements note, all signal requirements are guaranteed by design only. 12.1 absolute maximum ratings storage temperature........ ...........-65oc to +150oc ambient temperature ....................-65oc to +70oc supply voltage.......... ................ ......-0.3v to +3.6v environmental stresses above those listed in ab solute maximum ratings may cause permanent damage resulting in device failure. functionality at or abov e the limits listed below is not guaranteed. exposure to the environmental stress at the levels listed below for extended periods may adversely affect device reliability. 12.2 operating ranges commercial devices temperature (t a ) .............................. 0oc to +70oc supply voltages (v cc 3.3v) ................ +3.3v 5% supply voltages (v cc 2.5v) ................ +2.5v 5% input voltages ................... ....... +3.3v or +5v 5% operating ranges define the limits of guaranteed device functionality.
ip100a lf preliminary data sheet 93/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 dc characteristics dc characteristics are defined over commercial operating ranges unless specified otherwise. parameter symbol parameter description test conditions min typ max unit v cc 3.3v 3.3v power voltage 3.13 3.47 v i cc 3.3v 3.3v power current 10.6 ma v cc 2.5v 2.5v power voltage 2.37 2.63 v i cc 2.5v 2.5v power current 159.5 ma ttl i/o v ih input high voltage 2 v v il input low voltage 0.8 v i in input leakage current v in = v cc /gnd -10 10 a v oh output high voltage 2.4 v v ol output low voltage 0.4 v i ots output tri-state leakage 10 a 100base-tx receive v b rxp/rxn input bias voltage i ol = 4 ma 2.7 v r in rxp/rxn differential input resistance 6 k ? s on signal detect turn-on threshold 5 mhz square wave input 300 365 430 mv 100base-tx transmit (measured differentially after 1:1 transformer) v pdo peak differential output 50? from each output to vcc 0.95 1.05 v v oi output voltage imbalance 50? from each output to vcc 0.4 v overshoot 5 % v ref reference voltage of iset 1.25 v 10base-t receive v b10 rxp/rxm input bias voltage 1.4 v r in10 rxp/rxn differential input resistance 10 k ? v sq squelch threshold 5 mhz square wave 250 mv 10base-t transmit (measured different ially after the 1:1 transformer) v p peak differential output 50? from each output to vcc 2.2 2.8 v table 3 : dc characteristics
ip100a lf preliminary data sheet 94/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 12. 3 ac characteristics parameter symbol parameter description test conditions min typ max unit pci interface t rc rstn cycle 300 ns t rr rising edge or rstn to chip recovery 1 s t cc pciclk cycle 30 ns t ch pciclk high 11 ns t cl pciclk low 11 ns t rv pciclk rise to bused signal valid 2 11 ns t rvp pciclk rise to reqn, gntn valid 2 12 ns t rzo pciclk rise to signal on 2 ns t roz pciclk rise to signal off 28 ns t su bused signal setup wrt pciclk rise 7 ns t sup1 gntn setup wrt pciclk rise 10 ns t sup2 reqn setup wrt pciclk rise 12 ns t hd signal hold wrt pciclk rise 0 ns t rstoff rstn low to output signal float 40 ns eeprom interface t skc eesk cycle 1us - ns t skh eesk high 250 - ns t skl eesk low 250 - ns t cs eecs low 250 - ns t pd eedi valid wrt eesk rise 100 - ns t csk eecs setup wrt eesk rise 50 - ns t csh eecs hold wrt eesk fall 0 - ns t dos eedo setup wrt eesk rise 70 500 ns t doh eedo hold wrt eesk rise - 500 ns 100base-tx mdi t r /t f rise/fall time 3 5 ns t imb rise/fall time imbalance 0 500 ps t dcd duty cycle distortion 0.5 ns t j maximum output jitter (peak to peak) 0.7 1.4 ns 10base-t mdi t r10 /t f10 rise/fall time 25 ns t j10 transmit jitter 3.5 ns
ip100a lf preliminary data sheet 95/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 parameter symbol parameter description test conditions min typ max unit misc interface t cc clk25 cycle 40 40 ns t ch clk25 high 16 24 ns t cl clk25 low 16 24 ns table 4 : switching characteristics rstn pciclk reqn ip100a lf t rv bussed signals gntn any signal any signal t su t cl t sup2 t rvp t sup1 t rvp t rzo t hd t roz t rstoff t rc t cc t ch figure 16 : pci switching characteristics eecs eesk eedi eedo i p 100 a l f t csh t cs t cskv t skl t skc t skh t pd t dos t doh a7 a0 d15 d0 figure 17 : eeprom switching characteristics
ip100a lf preliminary data sheet 96/97 march. 30, 2007 copyright ? 2004, ic plus corp. ip100a lf-ds-r17 12. 4 thermal data theta ja theta jc conditions units 38.2 16 2 layer pcb o c/w 13 order information part no. package notice ip100a 128-pin qfp - ip100a lf 128-pin qfp lead free
ip100a lf preliminary data sheet 14 physical dimensions 128 pqfp outline dimensions 65 102 e b e 39 64 1 38 103 128 d l l 1 c a 2 a 1 gage plane h d h e d y unit: inches/mm dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a 1 0.010 0.014 0.018 0.25 0.35 0.45 a 2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 0.006 0.008 0.09 0.15 0.20 hd 0.669 0.677 0.685 17.00 17.20 17.40 d 0.547 0.551 0.555 13.90 14.00 14.10 he 0.906 0.913 0.921 23.00 23.20 23.40 e 0.783 0.787 0.791 19.90 20.00 20.10 e - 0.020 - - 0.50 - l 0.025 0.035 0.041 0.65 0.88 1.03 l 1 - 0.063 - - 1.60 - y - - 0.004 - - 0.10 0 - 12 0 - 12 note: 1. dimension d & e do not include mold protrusion. 2. dimension b does not include dambar protrusion. total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. ic plus corp. headquarters sales office 10f, no.47, lane 2, kwang-fu road, sec. 2, 4f, no. 106, hsin-tai-wu road, sec.1, hsin-chu city, taiwan 300, r.o.c. hsi-ch ih, taipei hsien, taiwan 221, r.o.c. tel: 886-3-575-0275 fax: 886-3-575-0475 tel: 886-2-2696-1669 fax: 886-2-2696-2220 website: www.icplus.com.tw march. 30, 2007 97/97 copyright ? 2004, ic plus corp. ip100a lf-ds-r17

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